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Rev 107 → Rev 110

/doc/or1ksim.info
1,5 → 1,5
This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
../../doc/or1ksim.texi.
This is ../../or1ksim/doc/or1ksim.info, produced by makeinfo version
4.13 from ../../or1ksim/doc/or1ksim.texi.
 
INFO-DIR-SECTION Embedded development
START-INFO-DIR-ENTRY
4294,55 → 4294,55
 

Tag Table:
Node: Top814
Node: Installation1224
Node: Preparation1471
Node: Configuring the Build1766
Node: Build and Install7490
Node: Known Issues8336
Node: Usage11398
Node: Standalone Simulator11612
Node: Profiling Utility14515
Node: Memory Profiling Utility15425
Node: Simulator Library16790
Node: Configuration24568
Node: Configuration File Format25177
Node: Configuration File Preprocessing25469
Node: Configuration File Syntax25840
Node: Simulator Configuration28625
Node: Simulator Behavior28916
Node: Verification API Configuration32960
Node: CUC Configuration34900
Node: Core OpenRISC Configuration36817
Node: CPU Configuration37319
Node: Memory Configuration41437
Node: Memory Management Configuration47895
Node: Cache Configuration50272
Node: Interrupt Configuration52658
Node: Power Management Configuration53394
Node: Branch Prediction Configuration54671
Node: Debug Interface Configuration56031
Node: Peripheral Configuration60251
Node: Memory Controller Configuration60877
Node: UART Configuration64291
Node: DMA Configuration67810
Node: Ethernet Configuration69677
Node: GPIO Configuration73653
Node: Display Interface Configuration75286
Node: Frame Buffer Configuration77595
Node: Keyboard Configuration79459
Node: Disc Interface Configuration81697
Node: Generic Peripheral Configuration86640
Node: Interactive Command Line88935
Node: Verification API95909
Node: Code Internals100339
Node: Coding Conventions100922
Node: Global Data Structures105349
Node: Concepts108006
Ref: Output Redirection108151
Node: Internal Debugging108690
Node: Regression Testing109214
Node: GNU Free Documentation License113009
Node: Index135416
Node: Top830
Node: Installation1240
Node: Preparation1487
Node: Configuring the Build1782
Node: Build and Install7506
Node: Known Issues8352
Node: Usage11414
Node: Standalone Simulator11628
Node: Profiling Utility14531
Node: Memory Profiling Utility15441
Node: Simulator Library16806
Node: Configuration24584
Node: Configuration File Format25193
Node: Configuration File Preprocessing25485
Node: Configuration File Syntax25856
Node: Simulator Configuration28641
Node: Simulator Behavior28932
Node: Verification API Configuration32976
Node: CUC Configuration34916
Node: Core OpenRISC Configuration36833
Node: CPU Configuration37335
Node: Memory Configuration41453
Node: Memory Management Configuration47911
Node: Cache Configuration50288
Node: Interrupt Configuration52674
Node: Power Management Configuration53410
Node: Branch Prediction Configuration54687
Node: Debug Interface Configuration56047
Node: Peripheral Configuration60267
Node: Memory Controller Configuration60893
Node: UART Configuration64307
Node: DMA Configuration67826
Node: Ethernet Configuration69693
Node: GPIO Configuration73669
Node: Display Interface Configuration75302
Node: Frame Buffer Configuration77611
Node: Keyboard Configuration79475
Node: Disc Interface Configuration81713
Node: Generic Peripheral Configuration86656
Node: Interactive Command Line88951
Node: Verification API95925
Node: Code Internals100355
Node: Coding Conventions100938
Node: Global Data Structures105365
Node: Concepts108022
Ref: Output Redirection108167
Node: Internal Debugging108706
Node: Regression Testing109230
Node: GNU Free Documentation License113025
Node: Index135432

End Tag Table
/doc/version.texi
1,4 → 1,4
@set UPDATED 2 June 2010
@set UPDATED 8 June 2010
@set UPDATED-MONTH June 2010
@set EDITION 2010-06-06
@set VERSION 2010-06-06
/ChangeLog
1,3 → 1,6
2010-06-08 Julius Baxter <julius.baxter@orsoc.se>
* peripherals/mc.h: Moved defines to peripherals/mc_defines.h
* peripherals/mc_defines.h: Created.
2010-06-06 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
/testsuite/test-code-or1k/eth/eth.h
0,0 → 1,170
/* eth.h -- OpenCores ethernet driver defines
 
Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
Copyright (C) 2008 Embecosm Limited
 
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
 
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
 
#ifndef ETH__H
#define ETH__H
 
/* Relative Register Addresses */
#define ETH_MODER (4 * 0x00)
#define ETH_INT_SOURCE (4 * 0x01)
#define ETH_INT_MASK (4 * 0x02)
#define ETH_IPGT (4 * 0x03)
#define ETH_IPGR1 (4 * 0x04)
#define ETH_IPGR2 (4 * 0x05)
#define ETH_PACKETLEN (4 * 0x06)
#define ETH_COLLCONF (4 * 0x07)
#define ETH_TX_BD_NUM (4 * 0x08)
#define ETH_CTRLMODER (4 * 0x09)
#define ETH_MIIMODER (4 * 0x0A)
#define ETH_MIICOMMAND (4 * 0x0B)
#define ETH_MIIADDRESS (4 * 0x0C)
#define ETH_MIITX_DATA (4 * 0x0D)
#define ETH_MIIRX_DATA (4 * 0x0E)
#define ETH_MIISTATUS (4 * 0x0F)
#define ETH_MAC_ADDR0 (4 * 0x10)
#define ETH_MAC_ADDR1 (4 * 0x11)
#define ETH_HASH0 (4 * 0x12)
#define ETH_HASH1 (4 * 0x13)
 
/* Where BD's are stored */
#define ETH_BD_BASE 0x400
#define ETH_BD_COUNT 0x100
#define ETH_BD_SPACE (4 * ETH_BD_COUNT)
 
/* Where to point DMA to transmit/receive */
#define ETH_DMA_RX_TX 0x800
 
/* Field definitions for MODER */
#define ETH_MODER_DMAEN_OFFSET 17
#define ETH_MODER_RECSMALL_OFFSET 16
#define ETH_MODER_PAD_OFFSET 15
#define ETH_MODER_HUGEN_OFFSET 14
#define ETH_MODER_CRCEN_OFFSET 13
#define ETH_MODER_DLYCRCEN_OFFSET 12
#define ETH_MODER_RST_OFFSET 11
#define ETH_MODER_FULLD_OFFSET 10
#define ETH_MODER_EXDFREN_OFFSET 9
#define ETH_MODER_NOBCKOF_OFFSET 8
#define ETH_MODER_LOOPBCK_OFFSET 7
#define ETH_MODER_IFG_OFFSET 6
#define ETH_MODER_PRO_OFFSET 5
#define ETH_MODER_IAM_OFFSET 4
#define ETH_MODER_BRO_OFFSET 3
#define ETH_MODER_NOPRE_OFFSET 2
#define ETH_MODER_TXEN_OFFSET 1
#define ETH_MODER_RXEN_OFFSET 0
 
/* Field definitions for INT_SOURCE */
#define ETH_INT_SOURCE_RXC_OFFSET 6
#define ETH_INT_SOURCE_TXC_OFFSET 5
#define ETH_INT_SOURCE_BUSY_OFFSET 4
#define ETH_INT_SOURCE_RXE_OFFSET 3
#define ETH_INT_SOURCE_RXB_OFFSET 2
#define ETH_INT_SOURCE_TXE_OFFSET 1
#define ETH_INT_SOURCE_TXB_OFFSET 0
 
/* Field definitions for INT_MASK */
#define ETH_INT_MASK_RXC_M_OFFSET 6
#define ETH_INT_MASK_TXC_M_OFFSET 5
#define ETH_INT_MASK_BUSY_M_OFFSET 4
#define ETH_INT_MASK_RXE_M_OFFSET 3
#define ETH_INT_MASK_RXB_M_OFFSET 2
#define ETH_INT_MASK_TXE_M_OFFSET 1
#define ETH_INT_MASK_TXB_M_OFFSET 0
 
/* Field definitions for PACKETLEN */
#define ETH_PACKETLEN_MINFL_OFFSET 16
#define ETH_PACKETLEN_MINFL_WIDTH 16
#define ETH_PACKETLEN_MAXFL_OFFSET 0
#define ETH_PACKETLEN_MAXFL_WIDTH 16
 
/* Field definitions for COLLCONF */
#define ETH_COLLCONF_MAXRET_OFFSET 16
#define ETH_COLLCONF_MAXRET_WIDTH 4
#define ETH_COLLCONF_COLLVALID_OFFSET 0
#define ETH_COLLCONF_COLLVALID_WIDTH 6
 
/* Field definitions for CTRLMODER */
#define ETH_CMODER_TXFLOW_OFFSET 2
#define ETH_CMODER_RXFLOW_OFFSET 1
#define ETH_CMODER_PASSALL_OFFSET 0
 
/* Field definitions for MIIMODER */
#define ETH_MIIMODER_MRST_OFFSET 9
#define ETH_MIIMODER_NOPRE_OFFSET 8
#define ETH_MIIMODER_CLKDIV_OFFSET 0
#define ETH_MIIMODER_CLKDIV_WIDTH 8
 
/* Field definitions for MIICOMMAND */
#define ETH_MIICOMM_WCDATA_OFFSET 2
#define ETH_MIICOMM_RSTAT_OFFSET 1
#define ETH_MIICOMM_SCANS_OFFSET 0
 
/* Field definitions for MIIADDRESS */
#define ETH_MIIADDR_RGAD_OFFSET 8
#define ETH_MIIADDR_RGAD_WIDTH 5
#define ETH_MIIADDR_FIAD_OFFSET 0
#define ETH_MIIADDR_FIAD_WIDTH 5
 
/* Field definitions for MIISTATUS */
#define ETH_MIISTAT_NVALID_OFFSET 1
#define ETH_MIISTAT_BUSY_OFFSET 1
#define ETH_MIISTAT_FAIL_OFFSET 0
 
/* Field definitions for TX buffer descriptors */
#define ETH_TX_BD_LENGTH_OFFSET 16
#define ETH_TX_BD_LENGTH_WIDTH 16
#define ETH_TX_BD_READY_OFFSET 15
#define ETH_TX_BD_IRQ_OFFSET 14
#define ETH_TX_BD_WRAP_OFFSET 13
#define ETH_TX_BD_PAD_OFFSET 12
#define ETH_TX_BD_CRC_OFFSET 11
#define ETH_TX_BD_LAST_OFFSET 10
#define ETH_TX_BD_PAUSE_OFFSET 9
#define ETH_TX_BD_UNDERRUN_OFFSET 8
#define ETH_TX_BD_RETRY_OFFSET 4
#define ETH_TX_BD_RETRY_WIDTH 4
#define ETH_TX_BD_RETRANSMIT_OFFSET 3
#define ETH_TX_BD_COLLISION_OFFSET 2
#define ETH_TX_BD_DEFER_OFFSET 1
#define ETH_TX_BD_NO_CARRIER_OFFSET 0
 
 
/* Field definitions for RX buffer descriptors */
#define ETH_RX_BD_LENGTH_OFFSET 16
#define ETH_RX_BD_LENGTH_WIDTH 16
#define ETH_RX_BD_READY_OFFSET 15
#define ETH_RX_BD_IRQ_OFFSET 14
#define ETH_RX_BD_WRAP_OFFSET 13
#define ETH_RX_BD_MISS_OFFSET 7
#define ETH_RX_BD_UVERRUN_OFFSET 6
#define ETH_RX_BD_INVALID_OFFSET 5
#define ETH_RX_BD_DRIBBLE_OFFSET 4
#define ETH_RX_BD_TOOBIG_OFFSET 3
#define ETH_RX_BD_TOOSHORT_OFFSET 2
#define ETH_RX_BD_CRC_OFFSET 1
#define ETH_RX_BD_COLLISION_OFFSET 0
 
#endif
/testsuite/test-code-or1k/eth/Makefile.am
29,8 → 29,6
 
eth_SOURCES = eth.c
 
eth_CPPFLAGS = -I$(srcdir)/../../../peripheral
 
eth_LDFLAGS = -T$(srcdir)/../default.ld
 
eth_LDADD = ../except/except.lo \
/testsuite/test-code-or1k/mc-dram/mc-dram.c
31,7 → 31,7
#include "mc-dram.h"
 
#include "config.h"
#include "mc.h"
#include "mc_defines.h"
#include "gpio.h"
#include "fields.h"
 
/testsuite/test-code-or1k/mc-ssram/mc-ssram.c
31,7 → 31,7
#include "mc-ssram.h"
 
#include "config.h"
#include "mc.h"
#include "mc_defines.h"
#include "gpio.h"
#include "fields.h"
 
/testsuite/test-code-or1k/ChangeLog
1,3 → 1,10
2010-06-08 Julius Baxter <julius.baxter@orsoc.se>
* eth/eth.h: Created from ethernet peripheral's header.
* eth/Makefile.am: Removed eth_CPPFLAGS.
* mc-sync/mc-sync.c: Changed include of mc.h to mc_defines.h
* mc-ssram/mc-ssram.c: Changed include of mc.h to mc_defines.h
* mc-dram/mc-dram.c: Changed include of mc.h to mc_defines.h
* mc-async/mc-async.c: Changed include of mc.h to mc_defines.h
2010-06-06 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Removed creation of lws-test makefile.
/testsuite/test-code-or1k/mc-sync/mc-sync.c
31,7 → 31,7
#include "mc-sync.h"
 
#include "config.h"
#include "mc.h"
#include "mc_defines.h"
#include "gpio.h"
#include "fields.h"
 
/testsuite/test-code-or1k/mc-async/mc-async.c
31,7 → 31,7
#include "mc-async.h"
 
#include "config.h"
#include "mc.h"
#include "mc_defines.h"
#include "gpio.h"
#include "fields.h"
 
/peripheral/mc_defines.h
0,0 → 1,114
/* mc_defines.h -- Defines for memory controller model
 
Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
Copyright (C) 2008 Embecosm Limited
 
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
 
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
 
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
/* This program is commented throughout in a fashion suitable for processing
with Doxygen. */
#ifndef MC_DEFINES__H
#define MC_DEFINES__H
 
#define N_CE 8
 
#define MC_CSR 0x00
#define MC_POC 0x04
#define MC_BA_MASK 0x08
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
#define MC_ADDR_SPACE (MC_CSC(N_CE))
 
/* POC register field definition */
#define MC_POC_EN_BW_OFFSET 0
#define MC_POC_EN_BW_WIDTH 2
#define MC_POC_EN_MEMTYPE_OFFSET 2
#define MC_POC_EN_MEMTYPE_WIDTH 2
 
/* CSC register field definition */
#define MC_CSC_EN_OFFSET 0
#define MC_CSC_MEMTYPE_OFFSET 1
#define MC_CSC_MEMTYPE_WIDTH 2
#define MC_CSC_BW_OFFSET 4
#define MC_CSC_BW_WIDTH 2
#define MC_CSC_MS_OFFSET 6
#define MC_CSC_MS_WIDTH 2
#define MC_CSC_WP_OFFSET 8
#define MC_CSC_BAS_OFFSET 9
#define MC_CSC_KRO_OFFSET 10
#define MC_CSC_PEN_OFFSET 11
#define MC_CSC_SEL_OFFSET 16
#define MC_CSC_SEL_WIDTH 8
 
#define MC_CSC_MEMTYPE_SDRAM 0
#define MC_CSC_MEMTYPE_SSRAM 1
#define MC_CSC_MEMTYPE_ASYNC 2
#define MC_CSC_MEMTYPE_SYNC 3
 
#define MC_CSR_VALID 0xFF000703LU
#define MC_POC_VALID 0x0000000FLU
#define MC_BA_MASK_VALID 0x000003FFLU
#define MC_CSC_VALID 0x00FF0FFFLU
#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
#define MC_TMS_SSRAM_VALID 0x00000000LU
#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
#define MC_TMS_SYNC_VALID 0x01FFFFFFLU
#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
 
/* TMS register field definition SDRAM */
#define MC_TMS_SDRAM_TRFC_OFFSET 24
#define MC_TMS_SDRAM_TRFC_WIDTH 4
#define MC_TMS_SDRAM_TRP_OFFSET 20
#define MC_TMS_SDRAM_TRP_WIDTH 4
#define MC_TMS_SDRAM_TRCD_OFFSET 17
#define MC_TMS_SDRAM_TRCD_WIDTH 4
#define MC_TMS_SDRAM_TWR_OFFSET 15
#define MC_TMS_SDRAM_TWR_WIDTH 2
#define MC_TMS_SDRAM_WBL_OFFSET 9
#define MC_TMS_SDRAM_OM_OFFSET 7
#define MC_TMS_SDRAM_OM_WIDTH 2
#define MC_TMS_SDRAM_CL_OFFSET 4
#define MC_TMS_SDRAM_CL_WIDTH 3
#define MC_TMS_SDRAM_BT_OFFSET 3
#define MC_TMS_SDRAM_BL_OFFSET 0
#define MC_TMS_SDRAM_BL_WIDTH 3
 
/* TMS register field definition ASYNC */
#define MC_TMS_ASYNC_TWWD_OFFSET 20
#define MC_TMS_ASYNC_TWWD_WIDTH 6
#define MC_TMS_ASYNC_TWD_OFFSET 16
#define MC_TMS_ASYNC_TWD_WIDTH 4
#define MC_TMS_ASYNC_TWPW_OFFSET 12
#define MC_TMS_ASYNC_TWPW_WIDTH 4
#define MC_TMS_ASYNC_TRDZ_OFFSET 8
#define MC_TMS_ASYNC_TRDZ_WIDTH 4
#define MC_TMS_ASYNC_TRDV_OFFSET 0
#define MC_TMS_ASYNC_TRDV_WIDTH 8
/* TMS register field definition SYNC */
#define MC_TMS_SYNC_TTO_OFFSET 16
#define MC_TMS_SYNC_TTO_WIDTH 9
#define MC_TMS_SYNC_TWR_OFFSET 12
#define MC_TMS_SYNC_TWR_WIDTH 4
#define MC_TMS_SYNC_TRDZ_OFFSET 8
#define MC_TMS_SYNC_TRDZ_WIDTH 4
#define MC_TMS_SYNC_TRDV_OFFSET 0
#define MC_TMS_SYNC_TRDV_WIDTH 8
 
#endif
/peripheral/mc.h
32,93 → 32,8
 
 
/* Constants. Also used by the test harness */
#define N_CE 8
#include "mc_defines.h"
 
#define MC_CSR 0x00
#define MC_POC 0x04
#define MC_BA_MASK 0x08
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
#define MC_ADDR_SPACE (MC_CSC(N_CE))
 
/* POC register field definition */
#define MC_POC_EN_BW_OFFSET 0
#define MC_POC_EN_BW_WIDTH 2
#define MC_POC_EN_MEMTYPE_OFFSET 2
#define MC_POC_EN_MEMTYPE_WIDTH 2
 
/* CSC register field definition */
#define MC_CSC_EN_OFFSET 0
#define MC_CSC_MEMTYPE_OFFSET 1
#define MC_CSC_MEMTYPE_WIDTH 2
#define MC_CSC_BW_OFFSET 4
#define MC_CSC_BW_WIDTH 2
#define MC_CSC_MS_OFFSET 6
#define MC_CSC_MS_WIDTH 2
#define MC_CSC_WP_OFFSET 8
#define MC_CSC_BAS_OFFSET 9
#define MC_CSC_KRO_OFFSET 10
#define MC_CSC_PEN_OFFSET 11
#define MC_CSC_SEL_OFFSET 16
#define MC_CSC_SEL_WIDTH 8
 
#define MC_CSC_MEMTYPE_SDRAM 0
#define MC_CSC_MEMTYPE_SSRAM 1
#define MC_CSC_MEMTYPE_ASYNC 2
#define MC_CSC_MEMTYPE_SYNC 3
 
#define MC_CSR_VALID 0xFF000703LU
#define MC_POC_VALID 0x0000000FLU
#define MC_BA_MASK_VALID 0x000003FFLU
#define MC_CSC_VALID 0x00FF0FFFLU
#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
#define MC_TMS_SSRAM_VALID 0x00000000LU
#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
#define MC_TMS_SYNC_VALID 0x01FFFFFFLU
#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
 
/* TMS register field definition SDRAM */
#define MC_TMS_SDRAM_TRFC_OFFSET 24
#define MC_TMS_SDRAM_TRFC_WIDTH 4
#define MC_TMS_SDRAM_TRP_OFFSET 20
#define MC_TMS_SDRAM_TRP_WIDTH 4
#define MC_TMS_SDRAM_TRCD_OFFSET 17
#define MC_TMS_SDRAM_TRCD_WIDTH 4
#define MC_TMS_SDRAM_TWR_OFFSET 15
#define MC_TMS_SDRAM_TWR_WIDTH 2
#define MC_TMS_SDRAM_WBL_OFFSET 9
#define MC_TMS_SDRAM_OM_OFFSET 7
#define MC_TMS_SDRAM_OM_WIDTH 2
#define MC_TMS_SDRAM_CL_OFFSET 4
#define MC_TMS_SDRAM_CL_WIDTH 3
#define MC_TMS_SDRAM_BT_OFFSET 3
#define MC_TMS_SDRAM_BL_OFFSET 0
#define MC_TMS_SDRAM_BL_WIDTH 3
 
/* TMS register field definition ASYNC */
#define MC_TMS_ASYNC_TWWD_OFFSET 20
#define MC_TMS_ASYNC_TWWD_WIDTH 6
#define MC_TMS_ASYNC_TWD_OFFSET 16
#define MC_TMS_ASYNC_TWD_WIDTH 4
#define MC_TMS_ASYNC_TWPW_OFFSET 12
#define MC_TMS_ASYNC_TWPW_WIDTH 4
#define MC_TMS_ASYNC_TRDZ_OFFSET 8
#define MC_TMS_ASYNC_TRDZ_WIDTH 4
#define MC_TMS_ASYNC_TRDV_OFFSET 0
#define MC_TMS_ASYNC_TRDV_WIDTH 8
/* TMS register field definition SYNC */
#define MC_TMS_SYNC_TTO_OFFSET 16
#define MC_TMS_SYNC_TTO_WIDTH 9
#define MC_TMS_SYNC_TWR_OFFSET 12
#define MC_TMS_SYNC_TWR_WIDTH 4
#define MC_TMS_SYNC_TRDZ_OFFSET 8
#define MC_TMS_SYNC_TRDZ_WIDTH 4
#define MC_TMS_SYNC_TRDV_OFFSET 0
#define MC_TMS_SYNC_TRDV_WIDTH 8
 
 
/* Prototypes for external use */
extern void mc_done ();
extern void reg_mc_sec ();

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