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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or1ksim
    from Rev 429 to Rev 430
    Reverse comparison

Rev 429 → Rev 430

/cpu/common/execute.h
58,7 → 58,6
int npc_not_valid; /*!< NPC updated while stalled */
oraddr_t pc; /*!< PC (and translated PC) */
oraddr_t pc_delay; /*!< Delay instr EA register */
uint32_t pic_lines; /*!< State of PIC lines */
struct iqueue_entry iqueue; /*!< Decode of just executed instr */
struct iqueue_entry icomplet; /*!< Decode of instr before this */
 
/cpu/or1k/sprs.c
154,6 → 154,8
break;
case SPR_PICSR:
if(!config.pic.edge_trigger)
/* When configured with level triggered interrupts we clear PICSR in PIC
when IRQ goes low */
cpu_state.sprs[SPR_PICSR] = prev_val;
break;
case SPR_PICMR:
/doc/or1ksim.info
1549,7 → 1549,23
If 1 (true, the default), the programmable interrupt controller is
edge triggered. If 0 (false), it is level triggered.
 
Note: When configured to be edge triggered, interrupts must
be cleared in the PICSR by the processor writing a '0' to the
appropriate bit.
 
When configured to be level triggered, the interrupt must be
cleared by lowering the peripheral's IRQ line. Writing '0' to
the PICSR has no effect.
 
Peripherals can call the function `report_interrupt' to
signal an interrupt request. When configured for level
triggered interrupts, the function `clear_interrupt' will
clear the appropriate bit in the PICSR. `clear_interrupt' has
no effect when Or1ksim is configured for edge triggered
interrupts - interrupts must be cleared by the processor
writing '0' to the appropriate bit in the PICSR in this case.
 
 

File: or1ksim.info, Node: Power Management Configuration, Next: Branch Prediction Configuration, Prev: Interrupt Configuration, Up: Core OpenRISC Configuration
 
4435,30 → 4451,30
Node: Memory Management Configuration51121
Node: Cache Configuration53498
Node: Interrupt Configuration55884
Node: Power Management Configuration56620
Node: Branch Prediction Configuration57897
Node: Debug Interface Configuration59257
Node: Peripheral Configuration61600
Node: Memory Controller Configuration62226
Node: UART Configuration66006
Node: DMA Configuration69525
Node: Ethernet Configuration71392
Node: GPIO Configuration75474
Node: Display Interface Configuration77107
Node: Frame Buffer Configuration79416
Node: Keyboard Configuration81280
Node: Disc Interface Configuration83518
Node: Generic Peripheral Configuration88622
Node: Interactive Command Line90917
Node: Verification API97891
Node: Code Internals102321
Node: Coding Conventions102904
Node: Global Data Structures107331
Node: Concepts109988
Ref: Output Redirection110133
Node: Internal Debugging110672
Node: Regression Testing111196
Node: GNU Free Documentation License114985
Node: Index137392
Node: Power Management Configuration57446
Node: Branch Prediction Configuration58723
Node: Debug Interface Configuration60083
Node: Peripheral Configuration62426
Node: Memory Controller Configuration63052
Node: UART Configuration66832
Node: DMA Configuration70351
Node: Ethernet Configuration72218
Node: GPIO Configuration76300
Node: Display Interface Configuration77933
Node: Frame Buffer Configuration80242
Node: Keyboard Configuration82106
Node: Disc Interface Configuration84344
Node: Generic Peripheral Configuration89448
Node: Interactive Command Line91743
Node: Verification API98717
Node: Code Internals103147
Node: Coding Conventions103730
Node: Global Data Structures108157
Node: Concepts110814
Ref: Output Redirection110959
Node: Internal Debugging111498
Node: Regression Testing112022
Node: GNU Free Documentation License115811
Node: Index138218

End Tag Table
/doc/or1ksim.texi
1893,6 → 1893,15
If 1 (true, the default), the programmable interrupt controller is
edge triggered. If 0 (false), it is level triggered.
 
@quotation Note
When configured to be edge triggered, interrupts must be cleared in the PICSR by the processor writing a '0' to the appropriate bit.
 
When configured to be level triggered, the interrupt must be cleared by lowering the peripheral's IRQ line. Writing '0' to the PICSR has no effect.
 
Peripherals can call the function @code{report_interrupt} to signal an interrupt request. When configured for level triggered interrupts, the function @code{clear_interrupt} will clear the appropriate bit in the PICSR. @code{clear_interrupt} has no effect when @value{OR1KSIM} is configured for edge triggered interrupts - interrupts must be cleared by the processor writing '0' to the appropriate bit in the PICSR in this case.
@end quotation
 
 
@end table
 
@node Power Management Configuration
/doc/version.texi
1,4 → 1,4
@set UPDATED 19 November 2010
@set UPDATED 22 November 2010
@set UPDATED-MONTH November 2010
@set EDITION 2010-11-11
@set VERSION 2010-11-11
/pic/pic.c
99,14 → 99,13
return;
}
 
if (cpu_state.pic_lines & lmask)
if (cpu_state.sprs[SPR_PICSR] & lmask)
{
/* No edge occured, warn about performance penalty and exit */
/* Interrupt already signaled and pending */
fprintf (stderr, "Warning: Int line %d did not change state\n", line);
return;
}
 
cpu_state.pic_lines |= lmask;
cpu_state.sprs[SPR_PICSR] |= lmask;
 
if ((cpu_state.sprs[SPR_PICMR] & lmask) || line < 2)
118,10 → 117,11
void
clear_interrupt (int line)
{
cpu_state.pic_lines &= ~(1 << line);
 
/* When level triggered, clear corresponding bit in PICSR */
if (!config.pic.edge_trigger)
cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
{
cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
}
}
 
/*----------------------------------------------------[ PIC configuration ]---*/
/ChangeLog
1,4 → 1,13
2010-11-22 Julius Baxter <julius@opencores.org>
* cpu/common/execute.h <cpu_state>: removed pic_lines variable.
* cpu/or1k/sprs.c: Added comment clarifying PICSR behavior.
* pic/pic.c: Removed use of pic_lines variable, added commenting
clarifying behavior.
<clear_interrupt>: only clear PICSR when level triggered.
* doc/or1ksim.texi (Interrupt Configuration): Added clarification of
interrupt behavior when edge or level triggered.
 
2010-11-22 Julius Baxter <julius@opencores.org>
* peripheral/eth.c (eth_miim_trans): comment out debug printf()s
* cpu/or32/generate.c (generate_body): Add except_handle call to all
generated illegal instruction cases.

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