URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or_debug_proxy/includes
- from Rev 39 to Rev 46
- ↔ Reverse comparison
Rev 39 → Rev 46
/usb_functions.h
74,6 → 74,7
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int usb_dbg_wb_read32(uint32_t adr, uint32_t *data); |
int usb_dbg_wb_read_block32(uint32_t adr, uint32_t *data, uint32_t len); |
int usb_dbg_wb_write8(uint32_t adr, uint8_t data); |
int usb_dbg_wb_write32(uint32_t adr, uint32_t data); |
int usb_dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len); |
int usb_dbg_cpu0_read(uint32_t adr, uint32_t *data); |
/or_debug_proxy.h
92,6 → 92,18
#define DC_CPU0 1 |
#define DC_CPU1 2 |
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// Defining access types for wishbone |
#define DBG_WB_WRITE8 0 |
#define DBG_WB_WRITE16 1 |
#define DBG_WB_WRITE32 2 |
#define DBG_WB_READ8 4 |
#define DBG_WB_READ16 5 |
#define DBG_WB_READ32 6 |
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// Defining access types for wishbone |
#define DBG_CPU_WRITE 2 |
#define DBG_CPU_READ 6 |
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// Manually figure the 5-bit reversed values again if they change |
#define DI_GO 0 |
#define DI_READ_CMD 1 |
118,6 → 130,8
int dbg_set_tap_ir(uint32_t ir); |
/* Set "scan chain" of debug unit (NOT JTAG TAP!) */ |
int dbg_set_chain(uint32_t chain); |
/* read a byte from wishbone */ |
int dbg_wb_write8(uint32_t adr, uint8_t data); |
/* read a word from wishbone */ |
int dbg_wb_read32(uint32_t adr, uint32_t *data); |
/* write a word to wishbone */ |