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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or_debug_proxy/includes
    from Rev 46 to Rev 47
    Reverse comparison

Rev 46 → Rev 47

/usb_functions.h
77,7 → 77,7
int usb_dbg_wb_write8(uint32_t adr, uint8_t data);
int usb_dbg_wb_write32(uint32_t adr, uint32_t data);
int usb_dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);
int usb_dbg_cpu0_read(uint32_t adr, uint32_t *data);
int usb_dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);
int usb_dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);
int usb_dbg_cpu0_write(uint32_t adr, uint32_t data);
int usb_dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);
int usb_dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);
/usb_driver_calls.h
86,5 → 86,4
FT2232_USB_JTAG_CloseDevice();
 
int init_usb_jtag();
 
 
void reinit_usb_jtag(void);
/or_debug_proxy.h
141,11 → 141,11
/* write a block to wishbone */
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);
/* read a register from cpu */
int dbg_cpu0_read(uint32_t adr, uint32_t *data);
int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);
/* read a register from cpu module */
int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);
/* write a cpu register */
int dbg_cpu0_write(uint32_t adr, uint32_t data);
int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);
/* write a cpu module register */
int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);
 

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