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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/bench/sysc/include
    from Rev 439 to Rev 462
    ↔ Reverse comparison
  •

Rev 439 → Rev 462

/RspPacket.h
31,46 → 31,40
 
#include <iostream>
 
 
//-----------------------------------------------------------------------------
//! Class for RSP packets
 
//! Can't be null terminated, since it may include zero bytes
//-----------------------------------------------------------------------------
class RspPacket
{
class RspPacket {
public:
 
//! The data buffer. Allow direct access to avoid unnecessary copying.
char *data;
//! The data buffer. Allow direct access to avoid unnecessary copying.
char *data;
 
// Constructor and destructor
RspPacket (int _bufSize);
~RspPacket ();
// Constructor and destructor
RspPacket(int _bufSize);
~RspPacket();
 
// Pack a constant string into a packet
void packStr (const char *str); // For fixed packets
// Accessors
int getBufSize ();
int getLen ();
void setLen (int _len);
// Pack a constant string into a packet
void packStr(const char *str); // For fixed packets
 
// Accessors
int getBufSize();
int getLen();
void setLen(int _len);
 
private:
 
//! The data buffer size
int bufSize;
//! The data buffer size
int bufSize;
 
//! Number of chars in the data buffer (<= bufSize)
int len;
//! Number of chars in the data buffer (<= bufSize)
int len;
 
};
 
 
//! Stream output
std::ostream &operator<< (std::ostream &s,
RspPacket &p);
std::ostream & operator<<(std::ostream & s, RspPacket & p);
 
 
#endif // RSP_PACKET_SC__H
#endif // RSP_PACKET_SC__H
/Utils.h
31,36 → 31,30
 
#include <stdint.h>
 
 
//-----------------------------------------------------------------------------
//! A class offering a number of convenience utilities for the GDB Server.
 
//! All static functions. This class is not intended to be instantiated.
//-----------------------------------------------------------------------------
class Utils
{
class Utils {
public:
 
static uint8_t char2Hex (int c);
static const char hex2Char (uint8_t d);
static void reg2Hex (uint32_t val,
char *buf);
static uint32_t hex2Reg (char *buf);
static void ascii2Hex (char *dest,
char *src);
static void hex2Ascii (char *dest,
char *src);
static int rspUnescape (char *buf,
int len);
static uint32_t htotl (uint32_t hostVal);
static uint32_t ttohl (uint32_t targetVal);
static uint8_t char2Hex(int c);
static const char hex2Char(uint8_t d);
static void reg2Hex(uint32_t val, char *buf);
static uint32_t hex2Reg(char *buf);
static void ascii2Hex(char *dest, char *src);
static void hex2Ascii(char *dest, char *src);
static int rspUnescape(char *buf, int len);
static uint32_t htotl(uint32_t hostVal);
static uint32_t ttohl(uint32_t targetVal);
 
 
private:
 
// Private constructor cannot be instantiated
Utils () {};
// Private constructor cannot be instantiated
Utils() {
};
 
}; // class Utils
}; // class Utils
 
#endif // UTILS_H
#endif // UTILS_H
/UartSC.h
30,30 → 30,28
 
//! Handle UART I/O
 
class UartSC
: public sc_core::sc_module
{
class UartSC:public sc_core::sc_module {
public:
 
// Constructor
UartSC (sc_core::sc_module_name name);
// Constructor
UartSC(sc_core::sc_module_name name);
 
// The ports
sc_in<bool> clk;
sc_in<bool> uarttx;
sc_out<bool> uartrx;
// The ports
sc_in < bool > clk;
sc_in < bool > uarttx;
sc_out < bool > uartrx;
 
// Init function
void initUart (int clk_freq_hz, int uart_baud) ;
// Transmit (from ORPSoC) handling function
void checkTx();
// Init function
void initUart(int clk_freq_hz, int uart_baud);
// Transmit (from ORPSoC) handling function
void checkTx();
 
private:
int clocks_per_bit;
uint8_t current_char;
int counter;
int bits_received;
int clocks_per_bit;
uint8_t current_char;
int counter;
int bits_received;
 
}; // UartSC ()
}; // UartSC ()
 
#endif // UART_SC__H
#endif // UART_SC__H
/JtagSC_includes.h
28,7 → 28,6
 
// $Id$
 
 
#include "JtagSC.h"
#include "TapActionDRScan.h"
#include "TapAction.h"
/MemCache.h
31,7 → 31,6
 
#include <stdint.h>
 
 
//! Module for cacheing memory accesses by the debug unit
 
//! Memory reads and writes through the Debug Unit via JTAG are time
46,33 → 45,29
//! In the event of a clash on write, the old value is replaced by the new
//! value.
 
class MemCache
{
class MemCache {
public:
 
// Constructor and destructor
MemCache (int _tableSize = 1009);
~MemCache ();
// Constructor and destructor
MemCache(int _tableSize = 1009);
~MemCache();
 
// Functions
void clear ();
void write (uint32_t addr,
uint32_t value);
bool read (uint32_t addr,
uint32_t &value);
// Functions
void clear();
void write(uint32_t addr, uint32_t value);
bool read(uint32_t addr, uint32_t & value);
 
private:
 
//! The size of the hash table. A prime number is a good choice.
int tableSize;
//! The size of the hash table. A prime number is a good choice.
int tableSize;
 
// The hash table, keyed by address. Done as three parallel vectors,
// allowing unambiguous clearing by use of memset for efficiency.
bool *tabIsValid;
uint32_t *tabKeyAddr;
uint32_t *tabValue;
// The hash table, keyed by address. Done as three parallel vectors,
// allowing unambiguous clearing by use of memset for efficiency.
bool *tabIsValid;
uint32_t *tabKeyAddr;
uint32_t *tabValue;
 
}; // MemCache ()
 
}; // MemCache ()
 
#endif // MEM_CACHE__H
#endif // MEM_CACHE__H
/elf.h
21,17 → 21,17
#endif
 
#ifdef OR32_TYPES
typedef uint32_t Elf32_Addr;
typedef uint16_t Elf32_Half;
typedef uint32_t Elf32_Off;
typedef int32_t Elf32_Sword;
typedef uint32_t Elf32_Word;
typedef uint32_t Elf32_Addr;
typedef uint16_t Elf32_Half;
typedef uint32_t Elf32_Off;
typedef int32_t Elf32_Sword;
typedef uint32_t Elf32_Word;
#else
typedef unsigned long Elf32_Addr;
typedef unsigned short Elf32_Half;
typedef unsigned long Elf32_Off;
typedef long Elf32_Sword;
typedef unsigned long Elf32_Word;
typedef unsigned long Elf32_Addr;
typedef unsigned short Elf32_Half;
typedef unsigned long Elf32_Off;
typedef long Elf32_Sword;
typedef unsigned long Elf32_Word;
#endif
 
/* These constants are for the segment types stored in the image headers */
61,7 → 61,7
#define EM_386 3
#define EM_68K 4
#define EM_88K 5
#define EM_486 6 /* Perhaps disused */
#define EM_486 6 /* Perhaps disused */
#define EM_860 7
 
#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
82,7 → 82,6
*/
#define EM_ALPHA 0x9026
 
 
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL 0
#define DT_NEEDED 1
127,37 → 126,36
 
/* Symbolic values for the entries in the auxiliary table
put on the initial stack */
#define AT_NULL 0 /* end of vector */
#define AT_IGNORE 1 /* entry should be ignored */
#define AT_EXECFD 2 /* file descriptor of program */
#define AT_PHDR 3 /* program headers for program */
#define AT_PHENT 4 /* size of program header entry */
#define AT_PHNUM 5 /* number of program headers */
#define AT_PAGESZ 6 /* system page size */
#define AT_BASE 7 /* base address of interpreter */
#define AT_FLAGS 8 /* flags */
#define AT_ENTRY 9 /* entry point of program */
#define AT_NOTELF 10 /* program is not ELF */
#define AT_UID 11 /* real uid */
#define AT_EUID 12 /* effective uid */
#define AT_GID 13 /* real gid */
#define AT_EGID 14 /* effective gid */
#define AT_NULL 0 /* end of vector */
#define AT_IGNORE 1 /* entry should be ignored */
#define AT_EXECFD 2 /* file descriptor of program */
#define AT_PHDR 3 /* program headers for program */
#define AT_PHENT 4 /* size of program header entry */
#define AT_PHNUM 5 /* number of program headers */
#define AT_PAGESZ 6 /* system page size */
#define AT_BASE 7 /* base address of interpreter */
#define AT_FLAGS 8 /* flags */
#define AT_ENTRY 9 /* entry point of program */
#define AT_NOTELF 10 /* program is not ELF */
#define AT_UID 11 /* real uid */
#define AT_EUID 12 /* effective uid */
#define AT_GID 13 /* real gid */
#define AT_EGID 14 /* effective gid */
 
 
typedef struct dynamic{
Elf32_Sword d_tag;
union{
Elf32_Sword d_val;
Elf32_Addr d_ptr;
} d_un;
typedef struct dynamic {
Elf32_Sword d_tag;
union {
Elf32_Sword d_val;
Elf32_Addr d_ptr;
} d_un;
} Elf32_Dyn;
 
typedef struct {
unsigned long long d_tag; /* entry tag value */
union {
unsigned long long d_val;
unsigned long long d_ptr;
} d_un;
unsigned long long d_tag; /* entry tag value */
union {
unsigned long long d_val;
unsigned long long d_ptr;
} d_un;
} Elf64_Dyn;
 
/* The following are used with relocations */
202,80 → 200,79
#define R_68K_RELATIVE 22
 
typedef struct elf32_rel {
Elf32_Addr r_offset;
Elf32_Word r_info;
Elf32_Addr r_offset;
Elf32_Word r_info;
} Elf32_Rel;
 
typedef struct elf64_rel {
unsigned long long r_offset; /* Location at which to apply the action */
unsigned long long r_info; /* index and type of relocation */
unsigned long long r_offset; /* Location at which to apply the action */
unsigned long long r_info; /* index and type of relocation */
} Elf64_Rel;
 
typedef struct elf32_rela{
Elf32_Addr r_offset;
Elf32_Word r_info;
Elf32_Sword r_addend;
typedef struct elf32_rela {
Elf32_Addr r_offset;
Elf32_Word r_info;
Elf32_Sword r_addend;
} Elf32_Rela;
 
typedef struct elf64_rela {
unsigned long long r_offset; /* Location at which to apply the action */
unsigned long long r_info; /* index and type of relocation */
unsigned long long r_addend; /* Constant addend used to compute value */
unsigned long long r_offset; /* Location at which to apply the action */
unsigned long long r_info; /* index and type of relocation */
unsigned long long r_addend; /* Constant addend used to compute value */
} Elf64_Rela;
 
typedef struct elf32_sym{
Elf32_Word st_name;
Elf32_Addr st_value;
Elf32_Word st_size;
unsigned char st_info;
unsigned char st_other;
Elf32_Half st_shndx;
typedef struct elf32_sym {
Elf32_Word st_name;
Elf32_Addr st_value;
Elf32_Word st_size;
unsigned char st_info;
unsigned char st_other;
Elf32_Half st_shndx;
} Elf32_Sym;
 
typedef struct elf64_sym {
unsigned int st_name; /* Symbol name, index in string tbl */
unsigned char st_info; /* Type and binding attributes */
unsigned char st_other; /* No defined meaning, 0 */
unsigned short st_shndx; /* Associated section index */
unsigned long long st_value; /* Value of the symbol */
unsigned long long st_size; /* Associated symbol size */
unsigned int st_name; /* Symbol name, index in string tbl */
unsigned char st_info; /* Type and binding attributes */
unsigned char st_other; /* No defined meaning, 0 */
unsigned short st_shndx; /* Associated section index */
unsigned long long st_value; /* Value of the symbol */
unsigned long long st_size; /* Associated symbol size */
} Elf64_Sym;
 
 
#define EI_NIDENT 16
 
typedef struct elf32_hdr{
unsigned char e_ident[EI_NIDENT];
Elf32_Half e_type;
Elf32_Half e_machine;
Elf32_Word e_version;
Elf32_Addr e_entry; /* Entry point */
Elf32_Off e_phoff;
Elf32_Off e_shoff;
Elf32_Word e_flags;
Elf32_Half e_ehsize;
Elf32_Half e_phentsize;
Elf32_Half e_phnum;
Elf32_Half e_shentsize;
Elf32_Half e_shnum;
Elf32_Half e_shstrndx;
typedef struct elf32_hdr {
unsigned char e_ident[EI_NIDENT];
Elf32_Half e_type;
Elf32_Half e_machine;
Elf32_Word e_version;
Elf32_Addr e_entry; /* Entry point */
Elf32_Off e_phoff;
Elf32_Off e_shoff;
Elf32_Word e_flags;
Elf32_Half e_ehsize;
Elf32_Half e_phentsize;
Elf32_Half e_phnum;
Elf32_Half e_shentsize;
Elf32_Half e_shnum;
Elf32_Half e_shstrndx;
} Elf32_Ehdr;
 
typedef struct elf64_hdr {
unsigned char e_ident[16]; /* ELF "magic number" */
short int e_type;
short unsigned int e_machine;
int e_version;
unsigned long long e_entry; /* Entry point virtual address */
unsigned long long e_phoff; /* Program header table file offset */
unsigned long long e_shoff; /* Section header table file offset */
int e_flags;
short int e_ehsize;
short int e_phentsize;
short int e_phnum;
short int e_shentsize;
short int e_shnum;
short int e_shstrndx;
unsigned char e_ident[16]; /* ELF "magic number" */
short int e_type;
short unsigned int e_machine;
int e_version;
unsigned long long e_entry; /* Entry point virtual address */
unsigned long long e_phoff; /* Program header table file offset */
unsigned long long e_shoff; /* Section header table file offset */
int e_flags;
short int e_ehsize;
short int e_phentsize;
short int e_phnum;
short int e_shentsize;
short int e_shnum;
short int e_shstrndx;
} Elf64_Ehdr;
 
/* These constants define the permissions on sections in the program
284,26 → 281,26
#define PF_W 0x2
#define PF_X 0x1
 
typedef struct elf32_phdr{
Elf32_Word p_type;
Elf32_Off p_offset;
Elf32_Addr p_vaddr;
Elf32_Addr p_paddr;
Elf32_Word p_filesz;
Elf32_Word p_memsz;
Elf32_Word p_flags;
Elf32_Word p_align;
typedef struct elf32_phdr {
Elf32_Word p_type;
Elf32_Off p_offset;
Elf32_Addr p_vaddr;
Elf32_Addr p_paddr;
Elf32_Word p_filesz;
Elf32_Word p_memsz;
Elf32_Word p_flags;
Elf32_Word p_align;
} Elf32_Phdr;
 
typedef struct elf64_phdr {
int p_type;
int p_flags;
unsigned long long p_offset; /* Segment file offset */
unsigned long long p_vaddr; /* Segment virtual address */
unsigned long long p_paddr; /* Segment physical address */
unsigned long long p_filesz; /* Segment size in file */
unsigned long long p_memsz; /* Segment size in memory */
unsigned long long p_align; /* Segment alignment, file & memory */
int p_type;
int p_flags;
unsigned long long p_offset; /* Segment file offset */
unsigned long long p_vaddr; /* Segment virtual address */
unsigned long long p_paddr; /* Segment physical address */
unsigned long long p_filesz; /* Segment size in file */
unsigned long long p_memsz; /* Segment size in memory */
unsigned long long p_align; /* Segment alignment, file & memory */
} Elf64_Phdr;
 
/* sh_type */
339,34 → 336,34
#define SHN_ABS 0xfff1
#define SHN_COMMON 0xfff2
#define SHN_HIRESERVE 0xffff
 
typedef struct elf32_shdr {
Elf32_Word sh_name;
Elf32_Word sh_type;
Elf32_Word sh_flags;
Elf32_Addr sh_addr;
Elf32_Off sh_offset;
Elf32_Word sh_size;
Elf32_Word sh_link;
Elf32_Word sh_info;
Elf32_Word sh_addralign;
Elf32_Word sh_entsize;
Elf32_Word sh_name;
Elf32_Word sh_type;
Elf32_Word sh_flags;
Elf32_Addr sh_addr;
Elf32_Off sh_offset;
Elf32_Word sh_size;
Elf32_Word sh_link;
Elf32_Word sh_info;
Elf32_Word sh_addralign;
Elf32_Word sh_entsize;
} Elf32_Shdr;
 
typedef struct elf64_shdr {
unsigned int sh_name; /* Section name, index in string tbl */
unsigned int sh_type; /* Type of section */
unsigned long long sh_flags; /* Miscellaneous section attributes */
unsigned long long sh_addr; /* Section virtual addr at execution */
unsigned long long sh_offset; /* Section file offset */
unsigned long long sh_size; /* Size of section in bytes */
unsigned int sh_link; /* Index of another section */
unsigned int sh_info; /* Additional section information */
unsigned long long sh_addralign; /* Section alignment */
unsigned long long sh_entsize; /* Entry size if section holds table */
unsigned int sh_name; /* Section name, index in string tbl */
unsigned int sh_type; /* Type of section */
unsigned long long sh_flags; /* Miscellaneous section attributes */
unsigned long long sh_addr; /* Section virtual addr at execution */
unsigned long long sh_offset; /* Section file offset */
unsigned long long sh_size; /* Size of section in bytes */
unsigned int sh_link; /* Index of another section */
unsigned int sh_info; /* Additional section information */
unsigned long long sh_addralign; /* Section alignment */
unsigned long long sh_entsize; /* Entry size if section holds table */
} Elf64_Shdr;
 
#define EI_MAG0 0 /* e_ident[] indexes */
#define EI_MAG0 0 /* e_ident[] indexes */
#define EI_MAG1 1
#define EI_MAG2 2
#define EI_MAG3 3
375,7 → 372,7
#define EI_VERSION 6
#define EI_PAD 7
 
#define ELFMAG0 0x7f /* EI_MAG */
#define ELFMAG0 0x7f /* EI_MAG */
#define ELFMAG1 'E'
#define ELFMAG2 'L'
#define ELFMAG3 'F'
382,16 → 379,16
#define ELFMAG "\177ELF"
#define SELFMAG 4
 
#define ELFCLASSNONE 0 /* EI_CLASS */
#define ELFCLASSNONE 0 /* EI_CLASS */
#define ELFCLASS32 1
#define ELFCLASS64 2
#define ELFCLASSNUM 3
 
#define ELFDATANONE 0 /* e_ident[EI_DATA] */
#define ELFDATANONE 0 /* e_ident[EI_DATA] */
#define ELFDATA2LSB 1
#define ELFDATA2MSB 2
 
#define EV_NONE 0 /* e_version, EI_VERSION */
#define EV_NONE 0 /* e_version, EI_VERSION */
#define EV_CURRENT 1
#define EV_NUM 2
 
403,9 → 400,9
 
/* Note header in a PT_NOTE section */
typedef struct elf32_note {
Elf32_Word n_namesz; /* Name size */
Elf32_Word n_descsz; /* Content size */
Elf32_Word n_type; /* Content type */
Elf32_Word n_namesz; /* Name size */
Elf32_Word n_descsz; /* Content size */
Elf32_Word n_type; /* Content type */
} Elf32_Nhdr;
 
/* Note header in a PT_NOTE section */
415,9 → 412,9
* is only 32 bits.
*/
typedef struct elf64_note {
unsigned int n_namesz; /* Name size */
unsigned int n_descsz; /* Content size */
unsigned int n_type; /* Content type */
unsigned int n_namesz; /* Name size */
unsigned int n_descsz; /* Content size */
unsigned int n_type; /* Content type */
} Elf64_Nhdr;
 
#ifdef __mc68000__
429,7 → 426,7
 
#if ELF_CLASS == ELFCLASS32
 
extern Elf32_Dyn _DYNAMIC [];
extern Elf32_Dyn _DYNAMIC[];
#define elfhdr elf32_hdr
#define elf_phdr elf32_phdr
#define elf_note elf32_note
436,7 → 433,7
 
#else
 
extern Elf64_Dyn _DYNAMIC [];
extern Elf64_Dyn _DYNAMIC[];
#define elfhdr elf64_hdr
#define elf_phdr elf64_phdr
#define elf_note elf64_note
443,5 → 440,4
 
#endif
 
 
#endif /* _LINUX_ELF_H */
/MemoryLoad.h
24,7 → 24,6
/* Here we define some often used caharcters in assembly files. This wil
probably go into architecture dependent directory. */
 
 
#ifndef MEMORYLOAD__H
#define MEMORYLOAD__H
 
41,9 → 40,9
#define PRINTF(x...)
 
/* Basic types for openrisc */
typedef uint32_t oraddr_t; /*!< Address as addressed by openrisc */
typedef uint32_t uorreg_t; /*!< An unsigned register of openrisc */
typedef int32_t orreg_t; /*!< A signed register of openrisc */
typedef uint32_t oraddr_t; /*!< Address as addressed by openrisc */
typedef uint32_t uorreg_t; /*!< An unsigned register of openrisc */
typedef int32_t orreg_t; /*!< A signed register of openrisc */
 
/* From abstract.h */
#define DEFAULT_MEMORY_START 0
73,8 → 72,6
#define ULONGEST unsigned long long
#endif /* ULONGEST */
 
 
 
#define PRIx32 "x"
#define PRIx16 "hx"
#define PRIx8 "hhx"
89,19 → 86,17
#define LE16(x) bswap_16(x)
 
/*! Instruction queue */
struct iqueue_entry
{
int insn_index;
uint32_t insn;
oraddr_t insn_addr;
struct iqueue_entry {
int insn_index;
uint32_t insn;
oraddr_t insn_addr;
};
 
/*! Structure for holding one label per particular memory location */
struct label_entry
{
char *name;
oraddr_t addr;
struct label_entry *next;
struct label_entry {
char *name;
oraddr_t addr;
struct label_entry *next;
};
 
/* from arch sim cpu/or1k/opcode/or32.h */
108,96 → 103,78
#define MAX_GPRS 32
#define PAGE_SIZE 8192
 
class MemoryLoad {
public:
 
// Constructor
MemoryLoad(OrpsocAccess * _accessor);
 
class MemoryLoad
{
public:
// Constructor
MemoryLoad(OrpsocAccess *_accessor);
// Label access function
struct label_entry *get_label(oraddr_t addr);
 
// Label access function
struct label_entry* get_label (oraddr_t addr);
uint32_t loadcode (char *filename,
oraddr_t startaddr,
oraddr_t virtphy_transl);
private:
//! The accessor for the Orpsoc instance
OrpsocAccess *accessor;
uint32_t loadcode(char *filename,
oraddr_t startaddr, oraddr_t virtphy_transl);
 
private:
 
//! The accessor for the Orpsoc instance
OrpsocAccess * accessor;
 
#define MEMORY_LEN 0x100000000ULL
/*!Whether to do immediate statistics. This seems to be for local debugging
of parse.c */
 
/*!Whether to do immediate statistics. This seems to be for local debugging
of parse.c */
#define IMM_STATS 0
/*!Unused mem memory marker. It is used when allocating program and data
memory during parsing */
unsigned int freemem;
/*!Translation table provided by microkernel. Only used if simulating
microkernel. */
oraddr_t transl_table;
/*!Used to signal whether during loading of programs a translation fault
occured. */
uint32_t transl_error;
 
/*!Unused mem memory marker. It is used when allocating program and data
memory during parsing */
unsigned int freemem;
 
/*!Translation table provided by microkernel. Only used if simulating
microkernel. */
oraddr_t transl_table;
 
/*!Used to signal whether during loading of programs a translation fault
occured. */
uint32_t transl_error;
 
#if IMM_STATS
int bcnt[33][3] = { 0 };
int bsum[3] = { 0 };
uint32_t movhi = 0;
#endif /* IMM_STATS */
int bcnt[33][3] = { 0 };
int bsum[3] = { 0 };
uint32_t movhi = 0;
#endif /* IMM_STATS */
 
// A large number, for the Linux kernel (~8000 functions)
// A large number, for the Linux kernel (~8000 functions)
#define LABELS_HASH_SIZE 10000
/* Local list of labels (symbols) */
struct label_entry *label_hash[LABELS_HASH_SIZE];
/* Local list of labels (symbols) */
struct label_entry *label_hash[LABELS_HASH_SIZE];
 
/* Function prototypes for external use */
char *strstrip (char *dst,
const char *src,
int n);
/* Function prototypes for external use */
char *strstrip(char *dst, const char *src, int n);
 
oraddr_t translate (oraddr_t laddr,
int *breakpoint);
int bits (uint32_t val);
void check_insn (uint32_t insn);
void addprogram (oraddr_t address,
uint32_t insn,
int *breakpoint);
void readfile_coff (char *filename,
short sections);
void readsyms_coff (char *filename,
uint32_t symptr,
uint32_t syms);
void readfile_elf (char *filename);
void identifyfile (char *filename);
oraddr_t translate(oraddr_t laddr, int *breakpoint);
 
void init_labels ();
void add_label (oraddr_t addr, char *name);
int bits(uint32_t val);
 
struct label_entry* find_label (char *name);
oraddr_t eval_label (char *name);
void check_insn(uint32_t insn);
 
void addprogram(oraddr_t address, uint32_t insn);
 
void readfile_coff(char *filename, short sections);
 
void readsyms_coff(char *filename, uint32_t symptr, uint32_t syms);
 
void readfile_elf(char *filename);
 
void identifyfile(char *filename);
 
void init_labels();
 
void add_label(oraddr_t addr, char *name);
 
struct label_entry *find_label(char *name);
oraddr_t eval_label(char *name);
 
};
 
#endif /* MEMORYLOAD__H */
#endif /* MEMORYLOAD__H */
/ResetSC.h
31,7 → 31,6
 
#include "systemc"
 
 
//! Provide a SystemC reset signal at startup
 
//! The reset signal is driven for a specified number of cycles after
38,27 → 37,24
//! creation. For convenience synchronous versions of the reset signal are
//! provided in both active high and active low formats.
 
class ResetSC
: public sc_core::sc_module
{
class ResetSC:public sc_core::sc_module {
public:
 
// Constructor
ResetSC (sc_core::sc_module_name name,
int _resetCounter = 5);
// Constructor
ResetSC(sc_core::sc_module_name name, int _resetCounter = 5);
 
// Method to drive the reset
void driveReset();
// Method to drive the reset
void driveReset();
 
// The ports
sc_core::sc_in<bool> clk;
sc_core::sc_out<bool> rst; // Active high reset
sc_core::sc_out<bool> rstn; // Active low reset
// The ports
sc_core::sc_in < bool > clk;
sc_core::sc_out < bool > rst; // Active high reset
sc_core::sc_out < bool > rstn; // Active low reset
 
private:
 
int resetCounter;
int resetCounter;
 
}; // ResetSC ()
}; // ResetSC ()
 
#endif // RESET_SC__H
#endif // RESET_SC__H
/GdbServerSC.h
41,193 → 41,186
#include "RspPacket.h"
#include "DebugUnitSC.h"
 
 
//! Module implementing a GDB RSP server.
 
//! A thread listens for RSP requests, which are converted to requests to read
//! and write registers, memory or control the CPU in the debug unit
 
class GdbServerSC
: public sc_core::sc_module
{
class GdbServerSC:public sc_core::sc_module {
public:
 
// Constructor and destructor
GdbServerSC (sc_core::sc_module_name name,
uint32_t _flashStart,
uint32_t _flashEnd,
int rspPort,
sc_core::sc_fifo<TapAction *> *tapActionQueue);
~GdbServerSC ();
// Constructor and destructor
GdbServerSC(sc_core::sc_module_name name,
uint32_t _flashStart,
uint32_t _flashEnd,
int rspPort,
sc_core::sc_fifo < TapAction * >*tapActionQueue);
~GdbServerSC();
 
private:
 
//! Definition of GDB target signals.
//! Definition of GDB target signals.
 
//! Data taken from the GDB 6.8 source. Only those we use defined here.
enum TargetSignal {
TARGET_SIGNAL_NONE = 0,
TARGET_SIGNAL_INT = 2,
TARGET_SIGNAL_ILL = 4,
TARGET_SIGNAL_TRAP = 5,
TARGET_SIGNAL_FPE = 8,
TARGET_SIGNAL_BUS = 10,
TARGET_SIGNAL_SEGV = 11,
TARGET_SIGNAL_ALRM = 14,
TARGET_SIGNAL_USR2 = 31,
TARGET_SIGNAL_PWR = 32
};
//! Data taken from the GDB 6.8 source. Only those we use defined here.
enum TargetSignal {
TARGET_SIGNAL_NONE = 0,
TARGET_SIGNAL_INT = 2,
TARGET_SIGNAL_ILL = 4,
TARGET_SIGNAL_TRAP = 5,
TARGET_SIGNAL_FPE = 8,
TARGET_SIGNAL_BUS = 10,
TARGET_SIGNAL_SEGV = 11,
TARGET_SIGNAL_ALRM = 14,
TARGET_SIGNAL_USR2 = 31,
TARGET_SIGNAL_PWR = 32
};
 
// Register numbering. Matches GDB client
static const int MAX_SPRS = 0x10000; //!< Max number of OR1K SPRs
static const int max_gprs = 32; //!< Max number of OR1K GPRs
// Register numbering. Matches GDB client
static const int MAX_SPRS = 0x10000; //!< Max number of OR1K SPRs
static const int max_gprs = 32; //!< Max number of OR1K GPRs
 
static const int PPC_REGNUM = max_gprs + 0; //!< Previous PC
static const int NPC_REGNUM = max_gprs + 1; //!< Next PC
static const int SR_REGNUM = max_gprs + 2; //!< Supervision Register
static const int PPC_REGNUM = max_gprs + 0; //!< Previous PC
static const int NPC_REGNUM = max_gprs + 1; //!< Next PC
static const int SR_REGNUM = max_gprs + 2; //!< Supervision Register
 
static const int NUM_REGS = max_gprs + 3; //!< Total GDB registers
static const int NUM_REGS = max_gprs + 3; //!< Total GDB registers
 
//! Maximum size of a GDB RSP packet
//static const int RSP_PKT_MAX = NUM_REGS * 8 + 1;
static const int RSP_PKT_MAX = 1024*16;
//! Maximum size of a GDB RSP packet
//static const int RSP_PKT_MAX = NUM_REGS * 8 + 1;
static const int RSP_PKT_MAX = 1024 * 16;
 
// OpenRISC exception addresses. Only the ones we need to know about
static const uint32_t EXCEPT_NONE = 0x000; //!< No exception
static const uint32_t EXCEPT_RESET = 0x100; //!< Reset
// OpenRISC exception addresses. Only the ones we need to know about
static const uint32_t EXCEPT_NONE = 0x000; //!< No exception
static const uint32_t EXCEPT_RESET = 0x100; //!< Reset
 
// SPR numbers
static const uint16_t SPR_NPC = 0x0010; //!< Next program counter
static const uint16_t SPR_SR = 0x0011; //!< Supervision register
static const uint16_t SPR_PPC = 0x0012; //!< Previous program counter
static const uint16_t SPR_GPR0 = 0x0400; //!< GPR 0
// SPR numbers
static const uint16_t SPR_NPC = 0x0010; //!< Next program counter
static const uint16_t SPR_SR = 0x0011; //!< Supervision register
static const uint16_t SPR_PPC = 0x0012; //!< Previous program counter
static const uint16_t SPR_GPR0 = 0x0400; //!< GPR 0
 
static const uint16_t SPR_DVR0 = 0x3000; //!< Debug value register 0
static const uint16_t SPR_DVR1 = 0x3001; //!< Debug value register 1
static const uint16_t SPR_DVR2 = 0x3002; //!< Debug value register 2
static const uint16_t SPR_DVR3 = 0x3003; //!< Debug value register 3
static const uint16_t SPR_DVR4 = 0x3004; //!< Debug value register 4
static const uint16_t SPR_DVR5 = 0x3005; //!< Debug value register 5
static const uint16_t SPR_DVR6 = 0x3006; //!< Debug value register 6
static const uint16_t SPR_DVR7 = 0x3007; //!< Debug value register 7
static const uint16_t SPR_DVR0 = 0x3000; //!< Debug value register 0
static const uint16_t SPR_DVR1 = 0x3001; //!< Debug value register 1
static const uint16_t SPR_DVR2 = 0x3002; //!< Debug value register 2
static const uint16_t SPR_DVR3 = 0x3003; //!< Debug value register 3
static const uint16_t SPR_DVR4 = 0x3004; //!< Debug value register 4
static const uint16_t SPR_DVR5 = 0x3005; //!< Debug value register 5
static const uint16_t SPR_DVR6 = 0x3006; //!< Debug value register 6
static const uint16_t SPR_DVR7 = 0x3007; //!< Debug value register 7
 
static const uint16_t SPR_DCR0 = 0x3008; //!< Debug control register 0
static const uint16_t SPR_DCR1 = 0x3009; //!< Debug control register 1
static const uint16_t SPR_DCR2 = 0x300a; //!< Debug control register 2
static const uint16_t SPR_DCR3 = 0x300b; //!< Debug control register 3
static const uint16_t SPR_DCR4 = 0x300c; //!< Debug control register 4
static const uint16_t SPR_DCR5 = 0x300d; //!< Debug control register 5
static const uint16_t SPR_DCR6 = 0x300e; //!< Debug control register 6
static const uint16_t SPR_DCR7 = 0x300f; //!< Debug control register 7
static const uint16_t SPR_DCR0 = 0x3008; //!< Debug control register 0
static const uint16_t SPR_DCR1 = 0x3009; //!< Debug control register 1
static const uint16_t SPR_DCR2 = 0x300a; //!< Debug control register 2
static const uint16_t SPR_DCR3 = 0x300b; //!< Debug control register 3
static const uint16_t SPR_DCR4 = 0x300c; //!< Debug control register 4
static const uint16_t SPR_DCR5 = 0x300d; //!< Debug control register 5
static const uint16_t SPR_DCR6 = 0x300e; //!< Debug control register 6
static const uint16_t SPR_DCR7 = 0x300f; //!< Debug control register 7
 
static const uint16_t SPR_DMR1 = 0x3010; //!< Debug mode register 1
static const uint16_t SPR_DMR2 = 0x3011; //!< Debug mode register 2
static const uint16_t SPR_DSR = 0x3014; //!< Debug stop register
static const uint16_t SPR_DRR = 0x3015; //!< Debug reason register
static const uint16_t SPR_DMR1 = 0x3010; //!< Debug mode register 1
static const uint16_t SPR_DMR2 = 0x3011; //!< Debug mode register 2
static const uint16_t SPR_DSR = 0x3014; //!< Debug stop register
static const uint16_t SPR_DRR = 0x3015; //!< Debug reason register
 
// SPR masks and offsets
static const uint32_t SPR_DMR1_ST = 0x00400000; //!< Single-step trace
static const uint32_t SPR_DMR2_WGB = 0x003ff000; //!< W/pt generating B/pt
static const uint32_t SPR_DMR2_WBS = 0xffc00000; //!< W/pt B/pt status
static const uint32_t SPR_DSR_TE = 0x00002000; //!< Trap
static const uint32_t SPR_DCR_DP_MASK = 0x00000001; //!< Debug Pair Present
static const uint32_t SPR_DCR_CC_MASK = 0x0000000e; //!< Compare Condition
static const uint32_t SPR_DCR_SC_MASK = 0x00000010; //!< Signed Comparison
static const uint32_t SPR_DCR_CT_MASK = 0x000000e0; //!< Compare To
static const uint32_t SPR_DMR2_WGB_SHIFT = 12; //!< W/pt Generate B/pt
// SPR masks and offsets
static const uint32_t SPR_DMR1_ST = 0x00400000; //!< Single-step trace
static const uint32_t SPR_DMR2_WGB = 0x003ff000; //!< W/pt generating B/pt
static const uint32_t SPR_DMR2_WBS = 0xffc00000; //!< W/pt B/pt status
static const uint32_t SPR_DSR_TE = 0x00002000; //!< Trap
static const uint32_t SPR_DCR_DP_MASK = 0x00000001; //!< Debug Pair Present
static const uint32_t SPR_DCR_CC_MASK = 0x0000000e; //!< Compare Condition
static const uint32_t SPR_DCR_SC_MASK = 0x00000010; //!< Signed Comparison
static const uint32_t SPR_DCR_CT_MASK = 0x000000e0; //!< Compare To
static const uint32_t SPR_DMR2_WGB_SHIFT = 12; //!< W/pt Generate B/pt
 
// DRR (Debug Reason Register) Bits
static const uint32_t SPR_DRR_RSTE = 0x00000001; //!< Reset
static const uint32_t SPR_DRR_BUSEE = 0x00000002; //!< Bus error
static const uint32_t SPR_DRR_DPFE = 0x00000004; //!< Data page fault
static const uint32_t SPR_DRR_IPFE = 0x00000008; //!< Insn page fault
static const uint32_t SPR_DRR_TTE = 0x00000010; //!< Tick timer
static const uint32_t SPR_DRR_AE = 0x00000020; //!< Alignment
static const uint32_t SPR_DRR_IIE = 0x00000040; //!< Illegal instruction
static const uint32_t SPR_DRR_IE = 0x00000080; //!< Interrupt
static const uint32_t SPR_DRR_DME = 0x00000100; //!< DTLB miss
static const uint32_t SPR_DRR_IME = 0x00000200; //!< ITLB miss
static const uint32_t SPR_DRR_RE = 0x00000400; //!< Range fault
static const uint32_t SPR_DRR_SCE = 0x00000800; //!< System call
static const uint32_t SPR_DRR_FPE = 0x00001000; //!< Floating point
static const uint32_t SPR_DRR_TE = 0x00002000; //!< Trap
 
// DRR (Debug Reason Register) Bits
static const uint32_t SPR_DRR_RSTE = 0x00000001; //!< Reset
static const uint32_t SPR_DRR_BUSEE = 0x00000002; //!< Bus error
static const uint32_t SPR_DRR_DPFE = 0x00000004; //!< Data page fault
static const uint32_t SPR_DRR_IPFE = 0x00000008; //!< Insn page fault
static const uint32_t SPR_DRR_TTE = 0x00000010; //!< Tick timer
static const uint32_t SPR_DRR_AE = 0x00000020; //!< Alignment
static const uint32_t SPR_DRR_IIE = 0x00000040; //!< Illegal instruction
static const uint32_t SPR_DRR_IE = 0x00000080; //!< Interrupt
static const uint32_t SPR_DRR_DME = 0x00000100; //!< DTLB miss
static const uint32_t SPR_DRR_IME = 0x00000200; //!< ITLB miss
static const uint32_t SPR_DRR_RE = 0x00000400; //!< Range fault
static const uint32_t SPR_DRR_SCE = 0x00000800; //!< System call
static const uint32_t SPR_DRR_FPE = 0x00001000; //!< Floating point
static const uint32_t SPR_DRR_TE = 0x00002000; //!< Trap
//! RSP Signal valu
uint32_t rsp_sigval;
 
//! RSP Signal valu
uint32_t rsp_sigval;
//! Trap instruction for OR32
static const uint32_t OR1K_TRAP_INSTR = 0x21000001;
 
//! Trap instruction for OR32
static const uint32_t OR1K_TRAP_INSTR = 0x21000001;
//! Thread ID used by Or1ksim
static const int OR1KSIM_TID = 1;
 
//! Thread ID used by Or1ksim
static const int OR1KSIM_TID = 1;
// The bounds of flash memory
uint32_t flashStart; //<! Start of flash memory
uint32_t flashEnd; //<! End of flash memory
 
// The bounds of flash memory
uint32_t flashStart; //<! Start of flash memory
uint32_t flashEnd; //<! End of flash memory
//! Our associated Debug Unit
DebugUnitSC *debugUnit;
 
//! Our associated Debug Unit
DebugUnitSC *debugUnit;
//! Our associated RSP interface (which we create)
RspConnection *rsp;
 
//! Our associated RSP interface (which we create)
RspConnection *rsp;
//! The packet pointer. There is only ever one packet in use at one time, so
//! there is no need to repeatedly allocate and delete it.
RspPacket *pkt;
 
//! The packet pointer. There is only ever one packet in use at one time, so
//! there is no need to repeatedly allocate and delete it.
RspPacket *pkt;
//! Hash table for matchpoints
MpHash *mpHash;
 
//! Hash table for matchpoints
MpHash *mpHash;
//! Is the target stopped
bool targetStopped;
 
//! Is the target stopped
bool targetStopped;
// SystemC thread to listen for and service RSP requests
void rspServer();
 
// SystemC thread to listen for and service RSP requests
void rspServer ();
// Main RSP request handler
void rspClientRequest();
 
// Main RSP request handler
void rspClientRequest ();
// Handle the various RSP requests
void rspCheckForException();
void rspReportException();
void rspContinue();
void rspContinue(uint32_t except);
void rspContinue(uint32_t addr, uint32_t except);
void rspInterrupt();
void rspReadAllRegs();
void rspWriteAllRegs();
void rspReadMem();
void rspWriteMem();
void rspReadReg();
void rspWriteReg();
void rspQuery();
void rspCommand();
void rspSet();
void rspRestart();
void rspStep();
void rspStep(uint32_t except);
void rspStep(uint32_t addr, uint32_t except);
void rspVpkt();
void rspWriteMemBin();
void rspRemoveMatchpoint();
void rspInsertMatchpoint();
 
// Handle the various RSP requests
void rspCheckForException();
void rspReportException ();
void rspContinue ();
void rspContinue (uint32_t except);
void rspContinue (uint32_t addr,
uint32_t except);
void rspInterrupt ();
void rspReadAllRegs ();
void rspWriteAllRegs ();
void rspReadMem ();
void rspWriteMem ();
void rspReadReg ();
void rspWriteReg ();
void rspQuery ();
void rspCommand ();
void rspSet ();
void rspRestart ();
void rspStep ();
void rspStep (uint32_t except);
void rspStep (uint32_t addr,
uint32_t except);
void rspVpkt ();
void rspWriteMemBin ();
void rspRemoveMatchpoint ();
void rspInsertMatchpoint ();
// Convenience wrappers for getting particular registers, which are really
// SPRs.
uint32_t readNpc();
void writeNpc(uint32_t addr);
 
// Convenience wrappers for getting particular registers, which are really
// SPRs.
uint32_t readNpc ();
void writeNpc (uint32_t addr);
uint32_t readGpr(int regNum);
void writeGpr(int regNum, uint32_t value);
 
uint32_t readGpr (int regNum);
void writeGpr (int regNum,
uint32_t value);
// Check if we got a message from the or1200 monitor module telling us
// to stall
bool checkMonitorPipe();
 
// Check if we got a message from the or1200 monitor module telling us
// to stall
bool checkMonitorPipe ();
}; // GdbServerSC ()
 
}; // GdbServerSC ()
 
#endif // GDB_SERVER_SC__H
#endif // GDB_SERVER_SC__H
/TapStateMachine.h
33,51 → 33,47
//! Last entry is not a state, but a marker of the number of states. Useful
//! for state transition matrices.
enum TapState {
TAP_TEST_LOGIC_RESET = 0,
TAP_RUN_TEST_IDLE = 1,
TAP_SELECT_DR_SCAN = 2,
TAP_CAPTURE_DR = 3,
TAP_SHIFT_DR = 4,
TAP_EXIT1_DR = 5,
TAP_PAUSE_DR = 6,
TAP_EXIT2_DR = 7,
TAP_UPDATE_DR = 8,
TAP_SELECT_IR_SCAN = 9,
TAP_CAPTURE_IR = 10,
TAP_SHIFT_IR = 11,
TAP_EXIT1_IR = 12,
TAP_PAUSE_IR = 13,
TAP_EXIT2_IR = 14,
TAP_UPDATE_IR = 15,
TAP_SIZE = 16
TAP_TEST_LOGIC_RESET = 0,
TAP_RUN_TEST_IDLE = 1,
TAP_SELECT_DR_SCAN = 2,
TAP_CAPTURE_DR = 3,
TAP_SHIFT_DR = 4,
TAP_EXIT1_DR = 5,
TAP_PAUSE_DR = 6,
TAP_EXIT2_DR = 7,
TAP_UPDATE_DR = 8,
TAP_SELECT_IR_SCAN = 9,
TAP_CAPTURE_IR = 10,
TAP_SHIFT_IR = 11,
TAP_EXIT1_IR = 12,
TAP_PAUSE_IR = 13,
TAP_EXIT2_IR = 14,
TAP_UPDATE_IR = 15,
TAP_SIZE = 16
}; // enum TapState
 
}; // enum TapState
 
 
//! Textual representation of all the TAP states.
 
//! Provided for debugging purposes
static const char *tapStateNames[TAP_SIZE] = {
"Test-Logic-Reset",
"Run-Test/Idle",
"Select-DR-Scan",
"Capture-DR",
"Shift-DR",
"Exit1-DR",
"Pause-DR",
"Exit2-DR",
"Update-DR",
"Select-IR-Scan",
"Capture-IR",
"Shift-IR",
"Exit1-IR",
"Pause-IR",
"Exit2-IR",
"Update-IR"
"Test-Logic-Reset",
"Run-Test/Idle",
"Select-DR-Scan",
"Capture-DR",
"Shift-DR",
"Exit1-DR",
"Pause-DR",
"Exit2-DR",
"Update-DR",
"Select-IR-Scan",
"Capture-IR",
"Shift-IR",
"Exit1-IR",
"Pause-IR",
"Exit2-IR",
"Update-IR"
}; // tapStateNames
 
}; // tapStateNames
 
 
//! TAP state machine
 
//! Tracks the state of the TAP. This should mirror the state of the TAP in
95,52 → 91,47
//! For convenience of users, this class provides a flag (resetDone::),
//! with accessors by which reset state can be recorded.
 
 
class TapStateMachine
{
class TapStateMachine {
public:
 
friend class JtagSC;
friend class TapAction;
friend class TapActionDRScan;
friend class TapActionIRScan;
friend class TapActionReset;
friend class JtagSC;
friend class TapAction;
friend class TapActionDRScan;
friend class TapActionIRScan;
friend class TapActionReset;
 
 
protected:
 
//! The number of cycles of TMS=1 required to force reset
static const int TAP_RESET_CYCLES = 5;
//! The number of cycles of TMS=1 required to force reset
static const int TAP_RESET_CYCLES = 5;
 
// Constructor
TapStateMachine();
// Constructor
TapStateMachine();
 
// Accessor for TAP state
TapState getState ();
// Accessor for TAP state
TapState getState();
 
// Accessors for TAP reset state
bool getResetDone ();
void setResetDone (bool _resetState);
// Accessors for TAP reset state
bool getResetDone();
void setResetDone(bool _resetState);
 
// Drive the TAP state machine
void nextState (bool tms);
// Drive the TAP state machine
void nextState(bool tms);
 
// Determine if we are in a particular target state
bool targetState (TapState target,
bool &tms);
// Determine if we are in a particular target state
bool targetState(TapState target, bool & tms);
 
private:
 
//! The current TAP state
TapState state;
//! The current TAP state
TapState state;
 
//! True if the TAP state machine has been through a reset.
//! True if the TAP state machine has been through a reset.
 
//! The state can be sure to match that of the target. Responsibility of
//! user classes to set this.
bool resetDone;
//! The state can be sure to match that of the target. Responsibility of
//! user classes to set this.
bool resetDone;
 
}; // class TapStateMachine
}; // class TapStateMachine
 
 
#endif // TAP_STATE_MACHINE__H
#endif // TAP_STATE_MACHINE__H
/OrpsocMain.h
46,6 → 46,10
#ifndef ORPSOC_MAIN__H
#define ORPSOC_MAIN__H
 
/* Globals used by other C modules */
extern bool gQuiet;
extern int gSimRunning;
 
//! The Verilog timescale unit (as SystemC timescale unit)
#define TIMESCALE_UNIT SC_NS
 
55,10 → 59,6
//! CPU clock Half period in timescale units
#define BENCH_CLK_HALFPERIOD 10
 
//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
//! Currently is 32MB (8M words)
#define ORPSOC_SRAM_SIZE (8388608*4)
 
//! Ratio of JTAG clock period to CPU clock period
#define CLOCK_RATIO 10
 
82,4 → 82,4
//! PPC, SR and NPC. Plus one byte for end of string marker.
#define RSP_MAX_PKT_SIZE ((32 + 3) * 8 + 1)
 
#endif // ORPSOC_MAIN__H
#endif // ORPSOC_MAIN__H
/JtagSC.h
34,7 → 34,6
#include "systemc"
#include "TapAction.h"
 
 
//! Default size of the FIFO queuing TAP actions
#define DEFAULT_TAP_FIFO_SIZE 256
 
68,44 → 67,40
//! the action owner of completion, through an sc_event, which is part of the
//! ::TapAction class.
//!
class JtagSC
: public sc_core::sc_module
{
class JtagSC:public sc_core::sc_module {
public:
 
// The ports. Note that the naming of the low level JTAG ports is reversed,
// because we are driving the inputs! */
sc_core::sc_in<bool> sysReset; //!< The system reset (active high)
// The ports. Note that the naming of the low level JTAG ports is reversed,
// because we are driving the inputs! */
sc_core::sc_in < bool > sysReset; //!< The system reset (active high)
 
sc_core::sc_in<bool> tck; //!< External JTAG TCK
sc_core::sc_out<bool> tdi; //!< JTAG TDI pin
sc_core::sc_in<bool> tdo; //!< JTAG TDO pin
sc_core::sc_out<bool> tms; //!< JTAG TMS pin
sc_core::sc_out<bool> trst; //!< JTAG TRST pin
sc_core::sc_in < bool > tck; //!< External JTAG TCK
sc_core::sc_out < bool > tdi; //!< JTAG TDI pin
sc_core::sc_in < bool > tdo; //!< JTAG TDO pin
sc_core::sc_out < bool > tms; //!< JTAG TMS pin
sc_core::sc_out < bool > trst; //!< JTAG TRST pin
 
//! JTAG action queue
sc_core::sc_fifo<TapAction *> *tapActionQueue;
//! JTAG action queue
sc_core::sc_fifo < TapAction * >*tapActionQueue;
 
// Constructor and destructor
JtagSC (sc_core::sc_module_name name,
int fifo_size = DEFAULT_TAP_FIFO_SIZE);
~JtagSC ();
// Constructor and destructor
JtagSC(sc_core::sc_module_name name,
int fifo_size = DEFAULT_TAP_FIFO_SIZE);
~JtagSC();
 
 
protected:
 
// Method to process the actions
void processActions();
// Method to process the actions
void processActions();
 
 
private:
 
//! The TAP state machine
TapStateMachine *stateMachine;
//! The TAP state machine
TapStateMachine * stateMachine;
 
//! The next TAP action
TapAction *currentTapAction;
//! The next TAP action
TapAction *currentTapAction;
 
}; // JtagSC ()
}; // JtagSC ()
 
#endif // JTAG_SC__H
#endif // JTAG_SC__H
/DebugUnitSC.h
29,7 → 29,6
#ifndef DEBUG_UNIT_SC__H
#define DEBUG_UNIT_SC__H
 
 
// Define if no cache is wanted
#define NOCACHE
 
42,7 → 41,6
#include "SprCache.h"
#include "MemCache.h"
 
 
//-----------------------------------------------------------------------------
//! Module modeling the OpenRISC 1000 Debug Unit
 
52,199 → 50,179
//! Provides a low level interface to the Embecosm SystemC JTAG interface,
//! queueing requests to read and write JTAG registers.
//-----------------------------------------------------------------------------
class DebugUnitSC
: public sc_core::sc_module
{
class DebugUnitSC:public sc_core::sc_module {
public:
 
// Constructor and destructor
DebugUnitSC (sc_core::sc_module_name name,
sc_core::sc_fifo<TapAction *> *_tapActionQueue);
~DebugUnitSC ();
// Constructor and destructor
DebugUnitSC(sc_core::sc_module_name name,
sc_core::sc_fifo < TapAction * >*_tapActionQueue);
~DebugUnitSC();
 
// Reset function for the debug unit
void resetDebugUnit ();
// Reset function for the debug unit
void resetDebugUnit();
 
// Functions to control and report on the CPU
void reset ();
void stall ();
void unstall ();
bool isStalled ();
// Functions to control and report on the CPU
void reset();
void stall();
void unstall();
bool isStalled();
 
// Functions to access SPRs
uint32_t readSpr (uint16_t sprNum);
void writeSpr (uint16_t sprNum,
uint32_t value);
void andSpr (uint16_t sprNum,
uint32_t value);
void orSpr (uint16_t sprNum,
uint32_t value);
// Functions to access SPRs
uint32_t readSpr(uint16_t sprNum);
void writeSpr(uint16_t sprNum, uint32_t value);
void andSpr(uint16_t sprNum, uint32_t value);
void orSpr(uint16_t sprNum, uint32_t value);
 
// Functions to access memory
uint32_t readMem32 (uint32_t addr);
bool writeMem32 (uint32_t addr,
uint32_t value);
uint8_t readMem8 (uint32_t addr);
bool writeMem8 (uint32_t addr,
uint8_t value);
// Functions to access memory
uint32_t readMem32(uint32_t addr);
bool writeMem32(uint32_t addr, uint32_t value);
uint8_t readMem8(uint32_t addr);
bool writeMem8(uint32_t addr, uint8_t value);
 
private:
 
// JTAG instructions
static const uint32_t CHAIN_SELECT_IR = 0x3; //!< Chain Select instruction
static const uint32_t DEBUG_IR = 0x8; //!< Debug instruction
// JTAG instructions
static const uint32_t CHAIN_SELECT_IR = 0x3; //!< Chain Select instruction
static const uint32_t DEBUG_IR = 0x8; //!< Debug instruction
 
//! JTAG instruction register length. There is no CRC for this register.
static const int JTAG_IR_LEN = 4; //!< JTAG instr reg length
//! JTAG instruction register length. There is no CRC for this register.
static const int JTAG_IR_LEN = 4; //!< JTAG instr reg length
 
// DEBUG UNIT CHAIN data register fields
static const int DUSEL_DR_LEN = 73; //!< total DUSEL DR size
static const int DUSEL_SEL_OFF = 0; //!< start of select field
static const int DUSEL_SEL_LEN = 1; //!< length of select field
static const int DUSEL_OPCODE_OFF = DUSEL_SEL_OFF + DUSEL_SEL_LEN; //!< start of opcode field
static const int DUSEL_OPCODE_LEN = 4; //!< length of opcode field
static const int DUSEL_CRC_OFF = DUSEL_OPCODE_OFF + DUSEL_OPCODE_LEN; //!< start of CRC field
static const int DUSEL_CRC_LEN = 32; //!< length of CRC field
static const int DUSEL_RESP_STATUS_OFF = DUSEL_CRC_OFF + DUSEL_CRC_LEN;
static const int DUSEL_RESP_STATUS_LEN = 4;
static const int DUSEL_RESP_CRC_OFF = DUSEL_RESP_STATUS_OFF + DUSEL_RESP_STATUS_LEN;
static const int DUSEL_RESP_CRC_LEN = 32;
// DEBUG UNIT CHAIN data register fields
static const int DUSEL_DR_LEN = 73; //!< total DUSEL DR size
static const int DUSEL_SEL_OFF = 0; //!< start of select field
static const int DUSEL_SEL_LEN = 1; //!< length of select field
static const int DUSEL_OPCODE_OFF = DUSEL_SEL_OFF + DUSEL_SEL_LEN; //!< start of opcode field
static const int DUSEL_OPCODE_LEN = 4; //!< length of opcode field
static const int DUSEL_CRC_OFF = DUSEL_OPCODE_OFF + DUSEL_OPCODE_LEN; //!< start of CRC field
static const int DUSEL_CRC_LEN = 32; //!< length of CRC field
static const int DUSEL_RESP_STATUS_OFF = DUSEL_CRC_OFF + DUSEL_CRC_LEN;
static const int DUSEL_RESP_STATUS_LEN = 4;
static const int DUSEL_RESP_CRC_OFF =
DUSEL_RESP_STATUS_OFF + DUSEL_RESP_STATUS_LEN;
static const int DUSEL_RESP_CRC_LEN = 32;
 
static const uint32_t DBG_CRC32_POLY = 0x04c11db7;
// OpenRISC 1000 scan chains (values in DUSEL data register field)
static const int OR1K_SC_UNDEF = -1; //!< Undefined OR1K scan chain
static const int OR1K_SC_WISHBONE = 0; //!< for memory access
static const int OR1K_SC_CPU0 = 1; //!< for access to CPU0
static const int OR1K_SC_CPU1 = 2; //!< for access to CPU1
static const uint32_t DBG_CRC32_POLY = 0x04c11db7;
 
// OpenRISC 1000 scan chains (values in DUSEL data register field)
static const int OR1K_SC_UNDEF = -1; //!< Undefined OR1K scan chain
static const int OR1K_SC_WISHBONE = 0; //!< for memory access
static const int OR1K_SC_CPU0 = 1; //!< for access to CPU0
static const int OR1K_SC_CPU1 = 2; //!< for access to CPU1
 
// JTAG RISC_DEBUG (for accessing SPR) data register fields
static const int RISC_DEBUG_DR_LEN = 74; //!< Total RISC_DEBUG DR size
static const int RISC_DEBUG_ADDR_OFF = 0; //!< start of address field
static const int RISC_DEBUG_ADDR_LEN = 32; //!< length of address field
static const int RISC_DEBUG_RW_OFF = 32; //!< start of read/write field
static const int RISC_DEBUG_RW_LEN = 1; //!< length of read/write field
static const int RISC_DEBUG_DATA_OFF = 33; //!< start of data field
static const int RISC_DEBUG_DATA_LEN = 32; //!< length of data field
static const int RISC_DEBUG_CRC_OFF = 65; //!< start of CRC field
static const int RISC_DEBUG_CRC_LEN = 8; //!< length of CRC field
static const int RISC_DEBUG_SPARE_OFF = 73; //!< start of spare bits
static const int RISC_DEBUG_SPARE_LEN = 1; //!< length of spare bit field
 
// JTAG RISC_DEBUG (for accessing SPR) data register fields
static const int RISC_DEBUG_DR_LEN = 74; //!< Total RISC_DEBUG DR size
static const int RISC_DEBUG_ADDR_OFF = 0; //!< start of address field
static const int RISC_DEBUG_ADDR_LEN = 32; //!< length of address field
static const int RISC_DEBUG_RW_OFF = 32; //!< start of read/write field
static const int RISC_DEBUG_RW_LEN = 1; //!< length of read/write field
static const int RISC_DEBUG_DATA_OFF = 33; //!< start of data field
static const int RISC_DEBUG_DATA_LEN = 32; //!< length of data field
static const int RISC_DEBUG_CRC_OFF = 65; //!< start of CRC field
static const int RISC_DEBUG_CRC_LEN = 8; //!< length of CRC field
static const int RISC_DEBUG_SPARE_OFF = 73; //!< start of spare bits
static const int RISC_DEBUG_SPARE_LEN = 1; //!< length of spare bit field
// JTAG REGISTER (for controlling the CPU) data register fields
static const int REGISTER_DR_LEN = 47; //!< Total REGISTER DR size
static const int REGISTER_ADDR_OFF = 0; //!< start of address field
static const int REGISTER_ADDR_LEN = 5; //!< length of address field
static const int REGISTER_RW_OFF = 5; //!< start of read/write field
static const int REGISTER_RW_LEN = 1; //!< length of read/write field
static const int REGISTER_DATA_OFF = 6; //!< start of data field
static const int REGISTER_DATA_LEN = 32; //!< length of data field
static const int REGISTER_CRC_OFF = 38; //!< start of CRC field
static const int REGISTER_CRC_LEN = 8; //!< length of CRC field
static const int REGISTER_SPARE_OFF = 46; //!< start of spare bits
static const int REGISTER_SPARE_LEN = 1; //!< length of spare bit field
 
// JTAG REGISTER (for controlling the CPU) data register fields
static const int REGISTER_DR_LEN = 47; //!< Total REGISTER DR size
static const int REGISTER_ADDR_OFF = 0; //!< start of address field
static const int REGISTER_ADDR_LEN = 5; //!< length of address field
static const int REGISTER_RW_OFF = 5; //!< start of read/write field
static const int REGISTER_RW_LEN = 1; //!< length of read/write field
static const int REGISTER_DATA_OFF = 6; //!< start of data field
static const int REGISTER_DATA_LEN = 32; //!< length of data field
static const int REGISTER_CRC_OFF = 38; //!< start of CRC field
static const int REGISTER_CRC_LEN = 8; //!< length of CRC field
static const int REGISTER_SPARE_OFF = 46; //!< start of spare bits
static const int REGISTER_SPARE_LEN = 1; //!< length of spare bit field
// Register addresses for the REGISTER scan chain
static const uint8_t OR1K_RSC_RISCOP = 0x04; //!< Used to reset/stall CPU
 
// Register addresses for the REGISTER scan chain
static const uint8_t OR1K_RSC_RISCOP = 0x04; //!< Used to reset/stall CPU
// Bits for the RISCOP register
static const uint32_t RISCOP_RESET = 0x00000001; //!< Reset the CPU
static const uint32_t RISCOP_STALL = 0x00000002; //!< Stall the CPU
 
// Bits for the RISCOP register
static const uint32_t RISCOP_RESET = 0x00000001; //!< Reset the CPU
static const uint32_t RISCOP_STALL = 0x00000002; //!< Stall the CPU
// JTAG WISHBONE (for accessing SPR) data register fields
static const int WISHBONE_DR_LEN = 74; //!< Total WISHBONE DR size
static const int WISHBONE_ADDR_OFF = 0; //!< start of address field
static const int WISHBONE_ADDR_LEN = 32; //!< length of address field
static const int WISHBONE_RW_OFF = 32; //!< start of read/write field
static const int WISHBONE_RW_LEN = 1; //!< length of read/write field
static const int WISHBONE_DATA_OFF = 33; //!< start of data field
static const int WISHBONE_DATA_LEN = 32; //!< length of data field
static const int WISHBONE_CRC_OFF = 65; //!< start of CRC field
static const int WISHBONE_CRC_LEN = 8; //!< length of CRC field
static const int WISHBONE_SPARE_OFF = 73; //!< start of spare bits
static const int WISHBONE_SPARE_LEN = 1; //!< length of spare bit field
 
// JTAG WISHBONE (for accessing SPR) data register fields
static const int WISHBONE_DR_LEN = 74; //!< Total WISHBONE DR size
static const int WISHBONE_ADDR_OFF = 0; //!< start of address field
static const int WISHBONE_ADDR_LEN = 32; //!< length of address field
static const int WISHBONE_RW_OFF = 32; //!< start of read/write field
static const int WISHBONE_RW_LEN = 1; //!< length of read/write field
static const int WISHBONE_DATA_OFF = 33; //!< start of data field
static const int WISHBONE_DATA_LEN = 32; //!< length of data field
static const int WISHBONE_CRC_OFF = 65; //!< start of CRC field
static const int WISHBONE_CRC_LEN = 8; //!< length of CRC field
static const int WISHBONE_SPARE_OFF = 73; //!< start of spare bits
static const int WISHBONE_SPARE_LEN = 1; //!< length of spare bit field
//! The NPC is special, so we need to know about it
static const int SPR_NPC = 0x10;
 
//! The NPC is special, so we need to know about it
static const int SPR_NPC = 0x10;
//! The JTAG fifo we queue on
sc_core::sc_fifo < TapAction * >*tapActionQueue;
 
//! The JTAG fifo we queue on
sc_core::sc_fifo<TapAction *> *tapActionQueue;
//! The processor stall state. When stalled we can use cacheing on
//! reads/writes of memory and SPRs.
enum {
UNKNOWN,
STALLED,
} stallState;
 
//! The processor stall state. When stalled we can use cacheing on
//! reads/writes of memory and SPRs.
enum {
UNKNOWN,
STALLED,
} stallState;
//! The currently selected scan chain
int currentScanChain;
 
//! The currently selected scan chain
int currentScanChain;
 
#ifdef NOCACHE
//! Even if no cached, we need to cache the NPC
uint32_t npcCachedValue;
//! Even if no cached, we need to cache the NPC
uint32_t npcCachedValue;
 
//! Cached NPC is valid
bool npcCacheIsValid;
//! Cached NPC is valid
bool npcCacheIsValid;
 
#else
//! The SPR cache
SprCache *sprCache;
//! The SPR cache
SprCache *sprCache;
 
//! The memory cache
MemCache *memCache;
//! The memory cache
MemCache *memCache;
#endif
 
// Functions to control the CPU
uint32_t readRiscop ();
void writeRiscop (uint32_t value);
// Functions to control the CPU
uint32_t readRiscop();
void writeRiscop(uint32_t value);
 
// Or1k JTAG actions
void selectDebugModule (int chain);
uint32_t readJtagReg (uint32_t addr);
uint32_t readJtagReg1 (uint32_t addr,
int bitSizeNoCrc);
uint32_t readJtagReg1 (uint64_t *dRegArray,
uint32_t addr,
int bitSizeNoCrc);
void writeJtagReg (uint32_t addr,
uint32_t data);
// Or1k JTAG actions
void selectDebugModule(int chain);
uint32_t readJtagReg(uint32_t addr);
uint32_t readJtagReg1(uint32_t addr, int bitSizeNoCrc);
uint32_t readJtagReg1(uint64_t * dRegArray,
uint32_t addr, int bitSizeNoCrc);
void writeJtagReg(uint32_t addr, uint32_t data);
 
// Utilities to pack and unpack bits to/from data registers.
void clearBits (uint64_t regArray[],
int regBits);
// Utilities to pack and unpack bits to/from data registers.
void clearBits(uint64_t regArray[], int regBits);
 
void packBits (uint64_t regArray[],
int fieldOffset,
int fieldBits,
uint64_t fieldVal);
void packBits(uint64_t regArray[],
int fieldOffset, int fieldBits, uint64_t fieldVal);
 
uint64_t unpackBits (uint64_t regArray[],
int fieldOffset,
int fieldBits);
uint64_t unpackBits(uint64_t regArray[],
int fieldOffset, int fieldBits);
 
// Utility to compute CRC-8 the OpenRISC way.
uint8_t crc8 (uint64_t dataArray[],
int size);
// Utility to compute CRC-32 for the debug unit
uint32_t crc32 (uint64_t dataArray[],
int size,
int offset);
// Utility to compute CRC-8 the OpenRISC way.
uint8_t crc8(uint64_t dataArray[], int size);
 
// Functions to bitreverse values
uint32_t bit_reverse_swar_2(uint32_t x);
uint32_t bit_reverse_swar_4(uint32_t x);
uint32_t bit_reverse_swar_8(uint32_t x);
uint32_t bit_reverse_swar_16(uint32_t x);
uint32_t bit_reverse_swar_32(uint32_t x);
// Utility to compute CRC-32 for the debug unit
uint32_t crc32(uint64_t dataArray[], int size, int offset);
 
// Functions to bitreverse values
uint32_t bit_reverse_swar_2(uint32_t x);
uint32_t bit_reverse_swar_4(uint32_t x);
uint32_t bit_reverse_swar_8(uint32_t x);
uint32_t bit_reverse_swar_16(uint32_t x);
uint32_t bit_reverse_swar_32(uint32_t x);
#define BITREV(x,y) bit_reverse_data(x,y)
uint32_t bit_reverse_data(uint32_t x, int length);
uint32_t bit_reverse_data(uint32_t x, int length);
 
}; // DebugUnitSC ()
 
 
}; // DebugUnitSC ()
 
#endif // DEBUG_UNIT_SC__H
#endif // DEBUG_UNIT_SC__H
/coff.h
11,11 → 11,10
more information about COFF, then O'Reilly has a very excellent book.
*/
 
#define E_SYMNMLEN 8 /* Number of characters in a symbol name */
#define E_FILNMLEN 14 /* Number of characters in a file name */
#define E_DIMNUM 4 /* Number of array dimensions in auxiliary entry */
 
#define E_SYMNMLEN 8 /* Number of characters in a symbol name */
#define E_FILNMLEN 14 /* Number of characters in a file name */
#define E_DIMNUM 4 /* Number of array dimensions in auxiliary entry */
 
/*
* These defines are byte order independent. There is no alignment of fields
* permitted in the structures. Therefore they are declared as characters
45,7 → 44,7
((unsigned long)((unsigned char)ps[2])<<16) |\
((unsigned long)((unsigned char)ps[1])<<8) |\
((unsigned long)((unsigned char)ps[0])))))
 
#define KEEP_ENDIAN_SHORT(ps) ((short)(((unsigned short)((unsigned char)ps[0])<<8)|\
((unsigned short)((unsigned char)ps[1]))))
 
64,7 → 63,6
 
/*** coff information for Intel 386/486. */
 
 
/*
* Bits for f_flags:
*
100,11 → 98,11
#define COFF_F_PATCH 0002000
#define COFF_F_NODF 0002000
 
#define COFF_I386MAGIC 0x14c /* Linux's system */
#define COFF_I386MAGIC 0x14c /* Linux's system */
 
#if 0 /* Perhaps, someday, these formats may be used. */
#if 0 /* Perhaps, someday, these formats may be used. */
#define COFF_I386PTXMAGIC 0x154
#define COFF_I386AIXMAGIC 0x175 /* IBM's AIX system */
#define COFF_I386AIXMAGIC 0x175 /* IBM's AIX system */
#define COFF_I386BADMAG(x) ((COFF_SHORT((x).f_magic) != COFF_I386MAGIC) \
&& COFF_SHORT((x).f_magic) != COFF_I386PTXMAGIC \
&& COFF_SHORT((x).f_magic) != COFF_I386AIXMAGIC)
114,15 → 112,14
 
/********************** FILE HEADER **********************/
 
struct coff_filehdr
{
char f_magic[2]; // magic number
char f_nscns[2]; // number of sections
char f_timdat[4]; // time & date stamp
char f_symptr[4]; // file pointer to symtab
char f_nsyms[4]; // number of symtab entries
char f_opthdr[2]; // sizeof(optional hdr)
char f_flags[2]; // flags
struct coff_filehdr {
char f_magic[2]; // magic number
char f_nscns[2]; // number of sections
char f_timdat[4]; // time & date stamp
char f_symptr[4]; // file pointer to symtab
char f_nsyms[4]; // number of symtab entries
char f_opthdr[2]; // sizeof(optional hdr)
char f_flags[2]; // flags
};
 
#define COFF_FILHDR struct coff_filehdr
142,16 → 139,15
*/
 
//typedef struct
struct COFF_aouthdr
{
char magic[2]; /* type of file */
char vstamp[2]; /* version stamp */
char tsize[4]; /* text size in bytes, padded to FW bdry */
char dsize[4]; /* initialized data " " */
char bsize[4]; /* uninitialized data " " */
char entry[4]; /* entry pt. */
char text_start[4]; /* base of text used for this file */
char data_start[4]; /* base of data used for this file */
struct COFF_aouthdr {
char magic[2]; /* type of file */
char vstamp[2]; /* version stamp */
char tsize[4]; /* text size in bytes, padded to FW bdry */
char dsize[4]; /* initialized data " " */
char bsize[4]; /* uninitialized data " " */
char entry[4]; /* entry pt. */
char text_start[4]; /* base of text used for this file */
char data_start[4]; /* base of data used for this file */
};
 
#define COFF_AOUTHDR COFF_aouthdr
159,42 → 155,42
 
#define COFF_STMAGIC 0401
#define COFF_OMAGIC 0404
#define COFF_JMAGIC 0407 /* dirty text and data image, can't share */
#define COFF_DMAGIC 0410 /* dirty text segment, data aligned */
#define COFF_ZMAGIC 0413 /* The proper magic number for executables */
#define COFF_JMAGIC 0407 /* dirty text and data image, can't share */
#define COFF_DMAGIC 0410 /* dirty text segment, data aligned */
#define COFF_ZMAGIC 0413 /* The proper magic number for executables */
#define COFF_SHMAGIC 0443 /* shared library header */
 
/********************** STORAGE CLASSES **********************/
 
/* This used to be defined as -1, but now n_sclass is unsigned. */
#define C_EFCN 0xff /* physical end of function */
#define C_EFCN 0xff /* physical end of function */
#define C_NULL 0
#define C_AUTO 1 /* automatic variable */
#define C_EXT 2 /* external symbol */
#define C_STAT 3 /* static */
#define C_REG 4 /* register variable */
#define C_EXTDEF 5 /* external definition */
#define C_LABEL 6 /* label */
#define C_ULABEL 7 /* undefined label */
#define C_MOS 8 /* member of structure */
#define C_ARG 9 /* function argument */
#define C_STRTAG 10 /* structure tag */
#define C_MOU 11 /* member of union */
#define C_UNTAG 12 /* union tag */
#define C_TPDEF 13 /* type definition */
#define C_USTATIC 14 /* undefined static */
#define C_ENTAG 15 /* enumeration tag */
#define C_MOE 16 /* member of enumeration */
#define C_REGPARM 17 /* register parameter */
#define C_FIELD 18 /* bit field */
#define C_AUTOARG 19 /* auto argument */
#define C_LASTENT 20 /* dummy entry (end of block) */
#define C_BLOCK 100 /* ".bb" or ".eb" */
#define C_FCN 101 /* ".bf" or ".ef" */
#define C_EOS 102 /* end of structure */
#define C_FILE 103 /* file name */
#define C_AUTO 1 /* automatic variable */
#define C_EXT 2 /* external symbol */
#define C_STAT 3 /* static */
#define C_REG 4 /* register variable */
#define C_EXTDEF 5 /* external definition */
#define C_LABEL 6 /* label */
#define C_ULABEL 7 /* undefined label */
#define C_MOS 8 /* member of structure */
#define C_ARG 9 /* function argument */
#define C_STRTAG 10 /* structure tag */
#define C_MOU 11 /* member of union */
#define C_UNTAG 12 /* union tag */
#define C_TPDEF 13 /* type definition */
#define C_USTATIC 14 /* undefined static */
#define C_ENTAG 15 /* enumeration tag */
#define C_MOE 16 /* member of enumeration */
#define C_REGPARM 17 /* register parameter */
#define C_FIELD 18 /* bit field */
#define C_AUTOARG 19 /* auto argument */
#define C_LASTENT 20 /* dummy entry (end of block) */
#define C_BLOCK 100 /* ".bb" or ".eb" */
#define C_FCN 101 /* ".bf" or ".ef" */
#define C_EOS 102 /* end of structure */
#define C_FILE 103 /* file name */
#define C_LINE 104 /* line # reformatted as symbol table entry */
#define C_ALIAS 105 /* duplicate tag */
#define C_ALIAS 105 /* duplicate tag */
#define C_HIDDEN 106 /* ext symbol in dmert public lib */
 
#define C_WEAKEXT 127 /* weak symbol -- GNU extension */
206,7 → 202,7
#define C_SYSTEM 23 /* System Wide variable */
 
/* New storage classes for WINDOWS_NT */
#define C_SECTION 104 /* section name */
#define C_SECTION 104 /* section name */
#define C_NT_WEAK 105 /* weak external */
 
/* New storage classes for 80960 */
217,14 → 213,14
#define C_SCALL 107 /* Procedure reachable via system call */
#define C_LEAFEXT 108 /* External leaf */
#define C_LEAFSTAT 113 /* Static leaf */
#define C_OPTVAR 109 /* Optimized variable */
#define C_DEFINE 110 /* Preprocessor #define */
#define C_PRAGMA 111 /* Advice to compiler or linker */
#define C_SEGMENT 112 /* 80960 segment name */
#define C_OPTVAR 109 /* Optimized variable */
#define C_DEFINE 110 /* Preprocessor #define */
#define C_PRAGMA 111 /* Advice to compiler or linker */
#define C_SEGMENT 112 /* 80960 segment name */
 
/* Storage classes for m88k */
#define C_SHADOW 107 /* shadow symbol */
#define C_VERSION 108 /* coff version symbol */
#define C_SHADOW 107 /* shadow symbol */
#define C_VERSION 108 /* coff version symbol */
 
/* New storage classes for RS/6000 */
#define C_HIDEXT 107 /* Un-named external symbol */
249,9 → 245,9
#define C_ESTAT (0x90)
 
/* Storage classes for Thumb symbols */
#define C_THUMBEXT (128 + C_EXT) /* 130 */
#define C_THUMBSTAT (128 + C_STAT) /* 131 */
#define C_THUMBLABEL (128 + C_LABEL) /* 134 */
#define C_THUMBEXT (128 + C_EXT) /* 130 */
#define C_THUMBSTAT (128 + C_STAT) /* 131 */
#define C_THUMBLABEL (128 + C_LABEL) /* 134 */
#define C_THUMBEXTFUNC (C_THUMBEXT + 20) /* 150 */
#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) /* 151 */
 
258,16 → 254,16
/********************** SECTION HEADER **********************/
 
struct COFF_scnhdr {
char s_name[8]; /* section name */
char s_paddr[4]; /* physical address, aliased s_nlib */
char s_vaddr[4]; /* virtual address */
char s_size[4]; /* section size */
char s_scnptr[4]; /* file ptr to raw data for section */
char s_relptr[4]; /* file ptr to relocation */
char s_lnnoptr[4]; /* file ptr to line numbers */
char s_nreloc[2]; /* number of relocation entries */
char s_nlnno[2]; /* number of line number entries */
char s_flags[4]; /* flags */
char s_name[8]; /* section name */
char s_paddr[4]; /* physical address, aliased s_nlib */
char s_vaddr[4]; /* virtual address */
char s_size[4]; /* section size */
char s_scnptr[4]; /* file ptr to raw data for section */
char s_relptr[4]; /* file ptr to relocation */
char s_lnnoptr[4]; /* file ptr to line numbers */
char s_nreloc[2]; /* number of relocation entries */
char s_nlnno[2]; /* number of line number entries */
char s_flags[4]; /* flags */
};
 
#define COFF_SCNHDR struct COFF_scnhdr
283,23 → 279,23
#define COFF_COMMENT ".comment"
#define COFF_LIB ".lib"
 
#define COFF_SECT_TEXT 0 /* Section for instruction code */
#define COFF_SECT_DATA 1 /* Section for initialized globals */
#define COFF_SECT_BSS 2 /* Section for un-initialized globals */
#define COFF_SECT_REQD 3 /* Minimum number of sections for good file */
#define COFF_SECT_TEXT 0 /* Section for instruction code */
#define COFF_SECT_DATA 1 /* Section for initialized globals */
#define COFF_SECT_BSS 2 /* Section for un-initialized globals */
#define COFF_SECT_REQD 3 /* Minimum number of sections for good file */
 
#define COFF_STYP_REG 0x00 /* regular segment */
#define COFF_STYP_DSECT 0x01 /* dummy segment */
#define COFF_STYP_NOLOAD 0x02 /* no-load segment */
#define COFF_STYP_GROUP 0x04 /* group segment */
#define COFF_STYP_PAD 0x08 /* .pad segment */
#define COFF_STYP_COPY 0x10 /* copy section */
#define COFF_STYP_TEXT 0x20 /* .text segment */
#define COFF_STYP_DATA 0x40 /* .data segment */
#define COFF_STYP_BSS 0x80 /* .bss segment */
#define COFF_STYP_INFO 0x200 /* .comment section */
#define COFF_STYP_OVER 0x400 /* overlay section */
#define COFF_STYP_LIB 0x800 /* library section */
#define COFF_STYP_REG 0x00 /* regular segment */
#define COFF_STYP_DSECT 0x01 /* dummy segment */
#define COFF_STYP_NOLOAD 0x02 /* no-load segment */
#define COFF_STYP_GROUP 0x04 /* group segment */
#define COFF_STYP_PAD 0x08 /* .pad segment */
#define COFF_STYP_COPY 0x10 /* copy section */
#define COFF_STYP_TEXT 0x20 /* .text segment */
#define COFF_STYP_DATA 0x40 /* .data segment */
#define COFF_STYP_BSS 0x80 /* .bss segment */
#define COFF_STYP_INFO 0x200 /* .comment section */
#define COFF_STYP_OVER 0x400 /* overlay section */
#define COFF_STYP_LIB 0x800 /* library section */
 
/*
* Shared libraries have the following section header in the data field for
307,8 → 303,8
*/
 
struct COFF_slib {
char sl_entsz[4]; /* Size of this entry */
char sl_pathndx[4]; /* size of the header field */
char sl_entsz[4]; /* Size of this entry */
char sl_pathndx[4]; /* size of the header field */
};
 
#define COFF_SLIBHD struct COFF_slib
323,11 → 319,11
*/
 
struct COFF_lineno {
union {
char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
char l_paddr[4]; /* (physical) address of line number */
} l_addr;
char l_lnno[2]; /* line number */
union {
char l_symndx[4]; /* function name symbol index, iff l_lnno == 0 */
char l_paddr[4]; /* (physical) address of line number */
} l_addr;
char l_lnno[2]; /* line number */
};
 
#define COFF_LINENO struct COFF_lineno
335,8 → 331,8
 
/********************** SYMBOLS **********************/
 
#define COFF_E_SYMNMLEN 8 /* # characters in a short symbol name */
#define COFF_E_FILNMLEN 14 /* # characters in a file name */
#define COFF_E_SYMNMLEN 8 /* # characters in a short symbol name */
#define COFF_E_FILNMLEN 14 /* # characters in a file name */
#define COFF_E_DIMNUM 4 /* # array dimensions in auxiliary entry */
 
/*
343,32 → 339,31
* All symbols and sections have the following definition
*/
 
struct COFF_syment
{
union {
char e_name[E_SYMNMLEN]; /* Symbol name (first 8 characters) */
struct {
char e_zeroes[4]; /* Leading zeros */
char e_offset[4]; /* Offset if this is a header section */
} e;
} e;
struct COFF_syment {
union {
char e_name[E_SYMNMLEN]; /* Symbol name (first 8 characters) */
struct {
char e_zeroes[4]; /* Leading zeros */
char e_offset[4]; /* Offset if this is a header section */
} e;
} e;
 
char e_value[4]; /* Value (address) of the segment */
char e_scnum[2]; /* Section number */
char e_type[2]; /* Type of section */
char e_sclass[1]; /* Loader class */
char e_numaux[1]; /* Number of auxiliary entries which follow */
char e_value[4]; /* Value (address) of the segment */
char e_scnum[2]; /* Section number */
char e_type[2]; /* Type of section */
char e_sclass[1]; /* Loader class */
char e_numaux[1]; /* Number of auxiliary entries which follow */
};
 
#define COFF_N_BTMASK (0xf) /* Mask for important class bits */
#define COFF_N_TMASK (0x30) /* Mask for important type bits */
#define COFF_N_BTSHFT (4) /* # bits to shift class field */
#define COFF_N_TSHIFT (2) /* # bits to shift type field */
#define COFF_N_BTMASK (0xf) /* Mask for important class bits */
#define COFF_N_TMASK (0x30) /* Mask for important type bits */
#define COFF_N_BTSHFT (4) /* # bits to shift class field */
#define COFF_N_TSHIFT (2) /* # bits to shift type field */
 
/*
* Auxiliary entries because the main table is too limiting.
*/
 
union COFF_auxent {
 
/*
375,65 → 370,65
* Debugger information
*/
 
struct {
char x_tagndx[4]; /* str, un, or enum tag indx */
union {
struct {
char x_lnno[2]; /* declaration line number */
char x_size[2]; /* str/union/array size */
} x_lnsz;
char x_fsize[4]; /* size of function */
} x_misc;
struct {
char x_tagndx[4]; /* str, un, or enum tag indx */
union {
struct {
char x_lnno[2]; /* declaration line number */
char x_size[2]; /* str/union/array size */
} x_lnsz;
char x_fsize[4]; /* size of function */
} x_misc;
 
union {
struct { /* if ISFCN, tag, or .bb */
char x_lnnoptr[4]; /* ptr to fcn line # */
char x_endndx[4]; /* entry ndx past block end */
} x_fcn;
union {
struct { /* if ISFCN, tag, or .bb */
char x_lnnoptr[4]; /* ptr to fcn line # */
char x_endndx[4]; /* entry ndx past block end */
} x_fcn;
 
struct { /* if ISARY, up to 4 dimen. */
char x_dimen[E_DIMNUM][2];
} x_ary;
} x_fcnary;
struct { /* if ISARY, up to 4 dimen. */
char x_dimen[E_DIMNUM][2];
} x_ary;
} x_fcnary;
 
char x_tvndx[2]; /* tv index */
} x_sym;
char x_tvndx[2]; /* tv index */
} x_sym;
 
/*
* Source file names (debugger information)
*/
 
union {
char x_fname[E_FILNMLEN];
struct {
char x_zeroes[4];
char x_offset[4];
} x_n;
} x_file;
union {
char x_fname[E_FILNMLEN];
struct {
char x_zeroes[4];
char x_offset[4];
} x_n;
} x_file;
 
/*
* Section information
*/
 
struct {
char x_scnlen[4]; /* section length */
char x_nreloc[2]; /* # relocation entries */
char x_nlinno[2]; /* # line numbers */
} x_scn;
struct {
char x_scnlen[4]; /* section length */
char x_nreloc[2]; /* # relocation entries */
char x_nlinno[2]; /* # line numbers */
} x_scn;
 
/*
* Transfer vector (branch table)
*/
struct {
char x_tvfill[4]; /* tv fill value */
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
} x_tv; /* info about .tv section (in auxent of symbol .tv)) */
 
struct {
char x_tvfill[4]; /* tv fill value */
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
} x_tv; /* info about .tv section (in auxent of symbol .tv)) */
};
 
#define COFF_SYMENT struct COFF_syment
#define COFF_SYMESZ 18
#define COFF_SYMESZ 18
#define COFF_AUXENT union COFF_auxent
#define COFF_AUXESZ 18
 
442,9 → 437,9
/********************** RELOCATION DIRECTIVES **********************/
 
struct COFF_reloc {
char r_vaddr[4]; /* Virtual address of item */
char r_symndx[4]; /* Symbol index in the symtab */
char r_type[2]; /* Relocation type */
char r_vaddr[4]; /* Virtual address of item */
char r_symndx[4]; /* Symbol index in the symtab */
char r_type[2]; /* Relocation type */
};
 
#define COFF_RELOC struct COFF_reloc
/TapActionDRScan.h
28,7 → 28,6
 
// $Id$
 
 
#ifndef TAP_ACTION_DR_SCAN__H
#define TAP_ACTION_DR_SCAN__H
 
37,7 → 36,6
#include "TapAction.h"
#include "TapStateMachine.h"
 
 
//! Class to represent a TAP DR-Scan action.
 
//! JTAG data registers can be huge and are represented generically as arrays
47,93 → 45,83
//! The SystemC classes for large unsigned ints are fabulously inefficient in
//! the reference implementation, so are not used here.
 
class TapActionDRScan
: public TapAction
{
class TapActionDRScan:public TapAction {
public:
 
// Constructors and destructor
TapActionDRScan (sc_core::sc_event *_doneEvent,
uint64_t _dRegInArray[],
int _dRegSize);
TapActionDRScan (sc_core::sc_event *_doneEvent,
uint64_t _dRegIn,
int _dRegSize);
TapActionDRScan (sc_core::sc_event *_doneEvent,
uint64_t _dRegInArray[],
int _dRegSize,
int _goToPauseState,
int _bitsBeforePauseState);
TapActionDRScan (sc_core::sc_event *_doneEvent,
uint64_t _dRegIn,
int _dRegSize,
int _goToPauseState,
int _bitsBeforePauseState);
~TapActionDRScan ();
// Constructors and destructor
TapActionDRScan(sc_core::sc_event * _doneEvent,
uint64_t _dRegInArray[], int _dRegSize);
TapActionDRScan(sc_core::sc_event * _doneEvent,
uint64_t _dRegIn, int _dRegSize);
TapActionDRScan(sc_core::sc_event * _doneEvent,
uint64_t _dRegInArray[],
int _dRegSize,
int _goToPauseState, int _bitsBeforePauseState);
TapActionDRScan(sc_core::sc_event * _doneEvent,
uint64_t _dRegIn,
int _dRegSize,
int _goToPauseState, int _bitsBeforePauseState);
~TapActionDRScan();
 
// Get the shifted out value
void getDRegOut (uint64_t dRegArray[]);
uint64_t getDRegOut ();
// Get the shifted out value
void getDRegOut(uint64_t dRegArray[]);
uint64_t getDRegOut();
 
 
protected:
 
// Process the action for IR-Scan
bool process (TapStateMachine *tapStateMachine,
bool &tdi,
bool tdo,
bool &tms);
// Process the action for IR-Scan
bool process(TapStateMachine * tapStateMachine,
bool & tdi, bool tdo, bool & tms);
 
 
private:
 
//! Number of bits in the data register
int dRegBitSize;
//! Number of bits in the data register
int dRegBitSize;
 
//! Number of uint64_t words in the data register
int dRegWordSize;
//! Number of uint64_t words in the data register
int dRegWordSize;
 
//! Mask for top word in multi-word register
uint64_t topMask;
//! Mask for top word in multi-word register
uint64_t topMask;
 
//! The value being shifted in
uint64_t *dRegInArray;
//! The value being shifted in
uint64_t *dRegInArray;
 
//! The value being shifted in (small version optimization)
uint64_t dRegIn;
//! The value being shifted in (small version optimization)
uint64_t dRegIn;
 
//! The value shifted out
uint64_t *dRegOutArray;
//! The value shifted out
uint64_t *dRegOutArray;
 
//! The value being shifted out (small version optimization)
uint64_t dRegOut;
//! The value being shifted out (small version optimization)
uint64_t dRegOut;
 
//! Should we go to PAUSE state and poll tdo during operation?
int goToPauseState;
//! Should we go to PAUSE state and poll tdo during operation?
int goToPauseState;
 
//! Number of bits to shift before going to PAUSE state and polling tdo
int bitsBeforePause;
//! Number of bits to shift before going to PAUSE state and polling tdo
int bitsBeforePause;
 
int pauseStateCount;
int pauseStateCount;
 
//! Bits shifted so far
int bitsShifted;
//! Bits shifted so far
int bitsShifted;
 
//! Where we are in the Shift-DR process
enum {
SHIFT_DR_PREPARING,
SHIFT_DR_SHIFTING,
SHIFT_DR_SHIFTING_BEFORE_PAUSE,
SHIFT_DR_SHIFTING_PAUSE,
SHIFT_DR_EXIT2,
SHIFT_DR_SHIFTING_AFTER_PAUSE,
SHIFT_DR_UPDATING
} dRScanState;
//! Where we are in the Shift-DR process
enum {
SHIFT_DR_PREPARING,
SHIFT_DR_SHIFTING,
SHIFT_DR_SHIFTING_BEFORE_PAUSE,
SHIFT_DR_SHIFTING_PAUSE,
SHIFT_DR_EXIT2,
SHIFT_DR_SHIFTING_AFTER_PAUSE,
SHIFT_DR_UPDATING
} dRScanState;
 
// Utilities to shift the bottom bit out and top bit in
bool shiftDRegOut ();
void shiftDRegIn (bool bitIn);
// Utilities to shift the bottom bit out and top bit in
bool shiftDRegOut();
void shiftDRegIn(bool bitIn);
 
}; // TapActionDRScan
}; // TapActionDRScan
 
#endif // TAP_ACTION_DR_SCAN__H
#endif // TAP_ACTION_DR_SCAN__H
/MpHash.h
31,75 → 31,63
 
#include <stdint.h>
 
 
//! Default size of the matchpoint hash table. Largest prime < 2^10
#define DEFAULT_MP_HASH_SIZE 1021
 
 
//! Enumeration of different types of matchpoint.
 
//! These have explicit values matching the second digit of 'z' and 'Z'
//! packets.
enum MpType {
BP_MEMORY = 0,
BP_HARDWARE = 1,
WP_WRITE = 2,
WP_READ = 3,
WP_ACCESS = 4
BP_MEMORY = 0,
BP_HARDWARE = 1,
WP_WRITE = 2,
WP_READ = 3,
WP_ACCESS = 4
};
 
 
class MpHash;
 
//! A structure for a matchpoint hash table entry
struct MpEntry
{
struct MpEntry {
public:
 
friend class MpHash; // The only one which can get at next
friend class MpHash; // The only one which can get at next
 
MpType type; //!< Type of matchpoint
uint32_t addr; //!< Address with the matchpoint
uint32_t instr; //!< Substituted instruction
MpType type; //!< Type of matchpoint
uint32_t addr; //!< Address with the matchpoint
uint32_t instr; //!< Substituted instruction
 
 
private:
 
MpEntry *next; //!< Next in this slot
MpEntry * next; //!< Next in this slot
};
 
 
//! A hash table for matchpoints
 
//! We do this as our own open hash table. Our keys are a pair of entities
//! (address and type), so STL map is not trivial to use.
 
class MpHash
{
class MpHash {
public:
 
// Constructor and destructor
MpHash (int _size = DEFAULT_MP_HASH_SIZE);
~MpHash ();
// Constructor and destructor
MpHash(int _size = DEFAULT_MP_HASH_SIZE);
~MpHash();
 
// Accessor methods
void add (MpType type,
uint32_t addr,
uint32_t instr);
MpEntry *lookup (MpType type,
uint32_t addr);
bool remove (MpType type,
uint32_t addr,
uint32_t *instr = NULL);
// Accessor methods
void add(MpType type, uint32_t addr, uint32_t instr);
MpEntry *lookup(MpType type, uint32_t addr);
bool remove(MpType type, uint32_t addr, uint32_t * instr = NULL);
 
private:
 
//! The hash table
MpEntry **hashTab;
//! The hash table
MpEntry ** hashTab;
 
//! Size of the hash table
int size;
//! Size of the hash table
int size;
 
};
 
#endif // MP_HASH__H
#endif // MP_HASH__H
/Or1200MonitorSC.h
44,51 → 44,48
//! wakes up on each posedge clock to check for "special" l.nop instructions,
//! which need processing.
 
class Or1200MonitorSC
: public sc_core::sc_module
{
class Or1200MonitorSC:public sc_core::sc_module {
public:
 
// Constructor
Or1200MonitorSC (sc_core::sc_module_name name,
OrpsocAccess *_accessor,
MemoryLoad *_memoryload,
int argc,
char *argv[]);
// Constructor
Or1200MonitorSC(sc_core::sc_module_name name,
OrpsocAccess * _accessor,
MemoryLoad * _memoryload, int argc, char *argv[]);
 
// Method to check instructions
void checkInstruction();
// Method to check instructions
void checkInstruction();
 
// Methods to setup and output state of processor to a file
void displayState();
void displayStateBinary();
// Methods to setup and output state of processor to a file
void displayState();
void displayStateBinary();
 
// Methods to generate the call and return list during execution
void callLog();
// Methods to generate trace to stdout
void printTrace();
 
// Method to calculate performance of the sim
void perfSummary();
// Methods to generate the call and return list during execution
void callLog();
 
// Method to print out the command-line switches for this module's options
void printSwitches();
// Method to calculate performance of the sim
void perfSummary();
 
// Method to print out the usage for each option
void printUsage();
// Method to dump simulation's RAM contents at finish
void memdump();
// Method to print out the command-line switches for this module's options
void printSwitches();
 
// Method used for monitoring and logging transactions on the system bus
//void busMonitor();
// Method to do simulator assisted printf'ing
void simPrintf(uint32_t stackaddr, uint32_t regparam);
// Method to print out the usage for each option
void printUsage();
 
// Method to dump simulation's RAM contents at finish
void memdump();
 
// Method used for monitoring and logging transactions on the system bus
//void busMonitor();
 
// The ports
sc_in<bool> clk;
// Method to do simulator assisted printf'ing
void simPrintf(uint32_t stackaddr, uint32_t regparam);
 
// The ports
sc_in < bool > clk;
 
private:
 
#define DEFAULT_EXEC_LOG_FILE "or1200_exec.log"
96,54 → 93,59
#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump"
#define DEFAULT_BUS_LOG_FILE "bus_trans.log"
 
// Special NOP instructions
static const uint32_t NOP_NOP = 0x15000000; //!< Normal nop instruction
static const uint32_t NOP_EXIT = 0x15000001; //!< End of simulation
static const uint32_t NOP_REPORT = 0x15000002; //!< Simple report
static const uint32_t NOP_PRINTF = 0x15000003; //!< Simprintf instruction
static const uint32_t NOP_PUTC = 0x15000004; //!< Putc instruction
static const uint32_t NOP_CNT_RESET = 0x15000005; //!< Reset statistics counters
static const uint32_t NOP_CNT_RESET1 = 0x15000007; /* Reset statistics counter 1 */
static const uint32_t NOP_CNT_RESET2 = 0x15000008; /* Reset statistics counter 2 */
static const uint32_t NOP_CNT_RESET3 = 0x15000009; /* Reset statistics counter 3 */
static const uint32_t NOP_MEM_STATS_RESET = 0x15000010; //!< Reset memory statistics counters
static const uint32_t NOP_CNT_RESET_DIFFERENCE = 0x15000006; //!< Reset stats counters, print
// Special NOP instructions
static const uint32_t NOP_NOP = 0; //!< Normal nop instruction
static const uint32_t NOP_EXIT = 1; //!< End of simulation
static const uint32_t NOP_REPORT = 2; //!< Simple report
static const uint32_t NOP_PRINTF = 3; //!< Simprintf instruction
static const uint32_t NOP_PUTC = 4; //!< Putc instruction
static const uint32_t NOP_CNT_RESET = 5; //!< Reset statistics counters
static const uint32_t NOP_GET_TICKS = 6; //!< Get # ticks running
static const uint32_t NOP_GET_PS = 7; //!< Get picosecs/cycle
 
// Variables for processor status output
ofstream statusFile;
ofstream profileFile;
bool profiling_enabled;
bool logging_enabled;
bool logfile_name_provided;
bool logging_regs;
bool binary_log_format;
bool quiet;
bool monitor_for_crash;
int lookslikewevecrashed_count, crash_monitor_buffer_head;
static const uint32_t NOP_CNT_RESET1 = 16; /* Reset statistics counter 1 */
static const uint32_t NOP_CNT_RESET2 = 17; /* Reset statistics counter 2 */
static const uint32_t NOP_CNT_RESET3 = 18; /* Reset statistics counter 3 */
static const uint32_t NOP_MEM_STATS_RESET = 32; //!< Reset memory statistics counters
static const uint32_t NOP_CNT_RESET_DIFFERENCE = 48; //!< Reset stats counters, print
 
// Variables for processor status output
ofstream statusFile;
ofstream profileFile;
bool profiling_enabled;
bool trace_enabled;
bool logging_enabled;
bool logfile_name_provided;
bool logging_regs;
bool binary_log_format;
bool perf_summary;
bool monitor_for_crash;
int lookslikewevecrashed_count, crash_monitor_buffer_head;
#define CRASH_MONITOR_BUFFER_SIZE 32
uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
bool wait_for_stall_cmd_response;
unsigned long long insn_count, insn_count_rst;
unsigned long long cycle_count, cycle_count_rst;
unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
ofstream memdumpFile;
string memdumpFileName;
bool do_memdump;
int memdump_start_addr, memdump_end_addr;
bool bus_trans_log_enabled, bus_trans_log_name_provided, bus_trans_log_start_delay_enable;
sc_time bus_trans_log_start_delay;
enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
ofstream busTransLog;
uint32_t crash_monitor_buffer[CRASH_MONITOR_BUFFER_SIZE][2]; //PC, Insn
bool wait_for_stall_cmd_response;
unsigned long long insn_count, insn_count_rst;
unsigned long long cycle_count, cycle_count_rst;
unsigned long long cycles_1, cycles_2, cycles_3; // Cycle counters for l.nop insns
ofstream memdumpFile;
string memdumpFileName;
bool do_memdump;
int memdump_start_addr, memdump_end_addr;
bool bus_trans_log_enabled, bus_trans_log_name_provided,
bus_trans_log_start_delay_enable;
sc_time bus_trans_log_start_delay;
enum busLogStates { BUS_LOG_IDLE, BUS_LOG_WAIT_FOR_ACK };
ofstream busTransLog;
 
//! Time measurement variable - for calculating performance of the sim
clock_t start;
//! Time measurement variable - for calculating performance of the sim
clock_t start;
 
//! The accessor for the Orpsoc instance
OrpsocAccess *accessor;
//! The accessor for the Orpsoc instance
OrpsocAccess *accessor;
 
//! The memory loading object
MemoryLoad *memoryload;
//! The memory loading object
MemoryLoad *memoryload;
 
}; // Or1200MonitorSC ()
}; // Or1200MonitorSC ()
 
#endif // OR1200_MONITOR_SC__H
#endif // OR1200_MONITOR_SC__H
/TapAction.h
28,27 → 28,21
 
// $Id$
 
 
#ifndef TAP_ACTION__H
#define TAP_ACTION__H
 
#include "TapStateMachine.h"
 
namespace sc_core
{
class sc_event;
namespace sc_core {
class sc_event;
}
 
 
//! Enumeration of all the TAP actions supported.
 
//! Enumeration of all the TAP actions supported.
enum TapActionType {
TAP_ACTION_RESET = 0,
TAP_ACTION_SHIFT_DR = 1,
TAP_ACTION_SHIFT_IR = 2
TAP_ACTION_RESET = 0,
TAP_ACTION_SHIFT_DR = 1,
TAP_ACTION_SHIFT_IR = 2
};
 
 
//! Abstract class to represent a TAP action.
 
//! Subclasses implement specific actions: Reset (TapActionReset::), DR-Scan
58,42 → 52,36
//! completion. Since we are not a SystemC class, we don't do the notification
//! ourselves.
 
class TapAction
{
class TapAction {
public:
 
friend class JtagSC;
friend class JtagSC;
 
// Constructor
TapAction (sc_core::sc_event *_doneEvent);
// Constructor
TapAction(sc_core::sc_event * _doneEvent);
 
 
protected:
 
// Accessor for the SystemC event to notify completion
sc_core::sc_event *getDoneEvent ();
// Accessor for the SystemC event to notify completion
sc_core::sc_event * getDoneEvent();
 
// Process the action. Pure virtual, so must be implemented by subclasses.
virtual bool process (TapStateMachine *tapStateMachine,
bool &tdi,
bool tdo,
bool &tms) = 0;
// Process the action. Pure virtual, so must be implemented by subclasses.
virtual bool process(TapStateMachine * tapStateMachine,
bool & tdi, bool tdo, bool & tms) = 0;
 
// Function to drive the TAP to a consistent state, optionally with a
// warning.
bool checkResetDone (TapStateMachine *tapStateMachine,
bool &tms,
bool warn = false);
// Function to drive the TAP to a consistent state, optionally with a
// warning.
bool checkResetDone(TapStateMachine * tapStateMachine,
bool & tms, bool warn = false);
 
 
private:
 
//! The associated SystemC event to mark completion
sc_core::sc_event *doneEvent;
//! The associated SystemC event to mark completion
sc_core::sc_event * doneEvent;
 
//! Counter for the reset process
int resetCounter;
//! Counter for the reset process
int resetCounter;
 
}; // TapAction ()
}; // TapAction ()
 
#endif // TAP_ACTION__H
#endif // TAP_ACTION__H
/TapActionIRScan.h
28,7 → 28,6
 
// $Id$
 
 
#ifndef TAP_ACTION_IR_SCAN__H
#define TAP_ACTION_IR_SCAN__H
 
37,7 → 36,6
#include "TapAction.h"
#include "TapStateMachine.h"
 
 
//! Class to represent a TAP IR-Scan action.
 
//! This class assumes that JTAG instruction registers are relatively
46,50 → 44,43
//! example uses 5 bits. 32-bits seems more than enough for the largest
//! applications.
 
class TapActionIRScan
: public TapAction
{
class TapActionIRScan:public TapAction {
public:
 
// Constructor
TapActionIRScan (sc_core::sc_event *_doneEvent,
uint32_t _iRegIn,
int _iRegSize);
// Constructor
TapActionIRScan(sc_core::sc_event * _doneEvent,
uint32_t _iRegIn, int _iRegSize);
 
// Get the shifted out value
uint32_t getIRegOut ();
// Get the shifted out value
uint32_t getIRegOut();
 
 
protected:
 
// Process the action for IR-Scan
bool process (TapStateMachine *tapStateMachine,
bool &tdi,
bool tdo,
bool &tms);
// Process the action for IR-Scan
bool process(TapStateMachine * tapStateMachine,
bool & tdi, bool tdo, bool & tms);
 
 
private:
 
//! The value being shifted in
uint32_t iRegIn;
//! The value being shifted in
uint32_t iRegIn;
 
//! The number of bits to shift
int iRegSize;
//! The number of bits to shift
int iRegSize;
 
//! The value shifted out
uint32_t iRegOut;
//! The value shifted out
uint32_t iRegOut;
 
//! The number of bits shifted so far
int bitsShifted;
//! The number of bits shifted so far
int bitsShifted;
 
//! Where we are in the IR-scan process
enum {
SHIFT_IR_PREPARING,
SHIFT_IR_SHIFTING,
SHIFT_IR_UPDATING
} iRScanState;
//! Where we are in the IR-scan process
enum {
SHIFT_IR_PREPARING,
SHIFT_IR_SHIFTING,
SHIFT_IR_UPDATING
} iRScanState;
 
}; // TapActionIRScan
}; // TapActionIRScan
 
#endif // TAP_ACTION_IR_SCAN__H
#endif // TAP_ACTION_IR_SCAN__H
/RspConnection.h
31,11 → 31,9
 
#include "RspPacket.h"
 
 
//! The default service to use if port number = 0 and no service specified
#define DEFAULT_RSP_SERVICE "or1ksim-rsp"
 
 
//-----------------------------------------------------------------------------
//! Class implementing the RSP connection listener
 
57,46 → 55,44
//! back to the client. Both must be non-blocking in the SystemC sense
//! (i.e. allow other SystemC threads to run).
//-----------------------------------------------------------------------------
class RspConnection
{
class RspConnection {
public:
 
// Constructors and destructor
RspConnection (int _portNum);
RspConnection (const char *_serviceName = DEFAULT_RSP_SERVICE);
~RspConnection ();
// Constructors and destructor
RspConnection(int _portNum);
RspConnection(const char *_serviceName = DEFAULT_RSP_SERVICE);
~RspConnection();
 
// Public interface: manage client connections
bool rspConnect ();
void rspClose ();
bool isConnected ();
char rspSocketPeek ();
// Public interface: get packets from the stream and put them out
bool getPkt (RspPacket *pkt);
bool putPkt (RspPacket *pkt);
int getRspChar ();
// Public interface: manage client connections
bool rspConnect();
void rspClose();
bool isConnected();
char rspSocketPeek();
 
// Public interface: get packets from the stream and put them out
bool getPkt(RspPacket * pkt);
bool putPkt(RspPacket * pkt);
 
int getRspChar();
 
private:
 
// Generic initializer
void rspInit (int _portNum,
const char *_serviceName);
// Generic initializer
void rspInit(int _portNum, const char *_serviceName);
 
// Internal routines to handle individual chars
bool putRspChar (char c);
//int getRspChar ();
// Internal routines to handle individual chars
bool putRspChar(char c);
//int getRspChar ();
 
//! The port number to listen on
int portNum;
//! The port number to listen on
int portNum;
 
//! The service name to listen on
const char *serviceName;
//! The service name to listen on
const char *serviceName;
 
//! The client file descriptor
int clientFd;
//! The client file descriptor
int clientFd;
 
}; // RspConnection ()
}; // RspConnection ()
 
#endif // RSP_CONNECTION__H
#endif // RSP_CONNECTION__H
/TraceSC.h
33,53 → 33,46
 
#include "Vorpsoc_top.h"
 
 
#if VM_TRACE
#include <SpTraceVcdC.h>
#endif
 
 
//! Class to drive the Verilator VCD trace interface.
 
//! Substantive code is only implemented if trace is enabled.
 
class TraceSC
: public sc_core::sc_module
{
class TraceSC:public sc_core::sc_module {
public:
 
// Constructor and destructor
TraceSC (sc_core::sc_module_name name,
Vorpsoc_top *_traceTarget,
int argc,
char * argv[]);
~TraceSC ();
// Constructor and destructor
TraceSC(sc_core::sc_module_name name,
Vorpsoc_top * _traceTarget, int argc, char *argv[]);
~TraceSC();
 
// Method to drive the trace
void driveTrace();
// Method to drive the trace
void driveTrace();
 
// VCD dump controling vars
int dump_start_delay, dump_stop_set;
int dumping_now;
sc_time dump_start,dump_stop;
/* The port */
//sc_in<bool> clk;
// VCD dump controling vars
int dump_start_delay, dump_stop_set;
int dumping_now;
sc_time dump_start, dump_stop;
 
/* The port */
//sc_in<bool> clk;
 
private:
 
//! The ORPSoC module we are tracing
Vorpsoc_top *traceTarget;
//! The ORPSoC module we are tracing
Vorpsoc_top * traceTarget;
 
 
#if VM_TRACE
//! The System Perl Trace file
SpTraceVcdCFile *spTraceFile;
//! The System Perl Trace file
SpTraceVcdCFile *spTraceFile;
#endif
 
// Set the time resolution
void setSpTimeResolution (sc_time t);
// Set the time resolution
void setSpTimeResolution(sc_time t);
 
}; // TraceSC ()
}; // TraceSC ()
 
#endif // TRACE_SC__H
#endif // TRACE_SC__H
/TapActionReset.h
28,7 → 28,6
 
// $Id$
 
 
#ifndef TAP_RESET_ACTION__H
#define TAP_RESET_ACTION__H
 
35,35 → 34,28
#include "TapAction.h"
#include "TapStateMachine.h"
 
 
//! Class to represent a TAP reset action.
 
//! This can be very simple, since it reuses the parent class method to do the
//! reset.
 
class TapActionReset
: public TapAction
{
class TapActionReset:public TapAction {
public:
 
// Constructor
TapActionReset (sc_core::sc_event *_doneEvent);
// Constructor
TapActionReset(sc_core::sc_event * _doneEvent);
 
 
protected:
 
// Process the action for reset
bool process (TapStateMachine *tapStateMachine,
bool &tdi,
bool tdo,
bool &tms);
// Process the action for reset
bool process(TapStateMachine * tapStateMachine,
bool & tdi, bool tdo, bool & tms);
 
 
private:
 
//!< Flag to mark first call to process method
bool firstTime;
//!< Flag to mark first call to process method
bool firstTime;
 
}; // TapActionReset
}; // TapActionReset
 
#endif // TAP_RESET_ACTION__H
#endif // TAP_RESET_ACTION__H
/OrpsocAccess.h
26,7 → 26,6
 
// $Id: OrpsocAccess.h 303 2009-02-16 11:20:17Z jeremy $
 
 
#ifndef ORPSOC_ACCESS__H
#define ORPSOC_ACCESS__H
 
46,75 → 45,73
// SoC Arbiter class - will also change if any modifications to bus architecture
//class Vorpsoc_top_wb_conbus_top__pi1;
 
 
//! Access functions to the Verilator model
 
//! This class encapsulates access to the Verilator model, allowing other
//! Classes to access model state, without needing to be built within the
//! Verilator environment.
class OrpsocAccess
{
class OrpsocAccess {
public:
 
// Constructor
OrpsocAccess (Vorpsoc_top *orpsoc_top);
// Constructor
OrpsocAccess(Vorpsoc_top * orpsoc_top);
 
// Accessor functions
bool getExFreeze ();
bool getWbFreeze ();
uint32_t getWbInsn ();
uint32_t getIdInsn ();
uint32_t getExInsn ();
uint32_t getWbPC ();
uint32_t getIdPC ();
uint32_t getExPC ();
bool getExceptFlushpipe ();
bool getExDslot ();
uint32_t getExceptType();
// Get a specific GPR from the register file
uint32_t getGpr (uint32_t regNum);
//SPR accessessors
uint32_t getSprSr ();
uint32_t getSprEpcr ();
uint32_t getSprEear ();
uint32_t getSprEsr ();
// Accessor functions
bool getExFreeze();
bool getWbFreeze();
uint32_t getWbInsn();
uint32_t getIdInsn();
uint32_t getExInsn();
uint32_t getWbPC();
uint32_t getIdPC();
uint32_t getExPC();
bool getExceptFlushpipe();
bool getExDslot();
uint32_t getExceptType();
// Get a specific GPR from the register file
uint32_t getGpr(uint32_t regNum);
void setGpr(uint32_t regNum, uint32_t value);
//SPR accessessors
uint32_t getSprSr();
uint32_t getSprEpcr();
uint32_t getSprEear();
uint32_t getSprEsr();
 
// Wishbone SRAM accessor functions
uint32_t get_mem32 (uint32_t addr);
uint8_t get_mem8 (uint32_t addr);
// Wishbone SRAM accessor functions
uint32_t get_mem32(uint32_t addr);
uint8_t get_mem8(uint32_t addr);
 
void set_mem32 (uint32_t addr, uint32_t data);
// Trigger a $readmemh for the RAM array
void do_ram_readmemh (void);
/*
// Arbiter access functions
uint8_t getWbArbGrant ();
// Master Signal Access functions
uint32_t getWbArbMastDatI (uint32_t mast_num);
uint32_t getWbArbMastDatO (uint32_t mast_num);
uint32_t getWbArbMastAdrI (uint32_t mast_num);
uint8_t getWbArbMastSelI (uint32_t mast_num);
uint8_t getWbArbMastSlaveSelDecoded (uint32_t mast_num);
bool getWbArbMastWeI (uint32_t mast_num);
bool getWbArbMastCycI (uint32_t mast_num);
bool getWbArbMastStbI (uint32_t mast_num);
bool getWbArbMastAckO (uint32_t mast_num);
bool getWbArbMastErrO (uint32_t mast_num);
*/
void set_mem32(uint32_t addr, uint32_t data);
// Trigger a $readmemh for the RAM array
void do_ram_readmemh(void);
/*
// Arbiter access functions
uint8_t getWbArbGrant ();
// Master Signal Access functions
uint32_t getWbArbMastDatI (uint32_t mast_num);
uint32_t getWbArbMastDatO (uint32_t mast_num);
uint32_t getWbArbMastAdrI (uint32_t mast_num);
uint8_t getWbArbMastSelI (uint32_t mast_num);
uint8_t getWbArbMastSlaveSelDecoded (uint32_t mast_num);
bool getWbArbMastWeI (uint32_t mast_num);
bool getWbArbMastCycI (uint32_t mast_num);
bool getWbArbMastStbI (uint32_t mast_num);
bool getWbArbMastAckO (uint32_t mast_num);
bool getWbArbMastErrO (uint32_t mast_num);
*/
 
 
private:
 
// Pointers to modules with accessor functions
Vorpsoc_top_or1200_ctrl *or1200_ctrl;
Vorpsoc_top_or1200_except *or1200_except;
Vorpsoc_top_or1200_sprs *or1200_sprs;
Vorpsoc_top_or1200_dpram *rf_a;
/*Vorpsoc_top_ram_wb_sc_sw*//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000*/ /*Vorpsoc_top_wb_ram_b3__D20_A17_M800000 *ram_wb_sc_sw;*/
Vorpsoc_top_ram_wb_b3__pi3 *wishbone_ram;
// Arbiter
//Vorpsoc_top_wb_conbus_top__pi1 *wb_arbiter;
// Pointers to modules with accessor functions
Vorpsoc_top_or1200_ctrl * or1200_ctrl;
Vorpsoc_top_or1200_except *or1200_except;
Vorpsoc_top_or1200_sprs *or1200_sprs;
Vorpsoc_top_or1200_dpram *rf_a;
/*Vorpsoc_top_ram_wb_sc_sw *//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000 *//*Vorpsoc_top_wb_ram_b3__D20_A17_M800000 *ram_wb_sc_sw; */
Vorpsoc_top_ram_wb_b3__pi3 *wishbone_ram;
// Arbiter
//Vorpsoc_top_wb_conbus_top__pi1 *wb_arbiter;
 
}; // OrpsocAccess ()
}; // OrpsocAccess ()
 
#endif // ORPSOC_ACCESS__H
#endif // ORPSOC_ACCESS__H
/JtagDriverSC.h
35,104 → 35,92
 
#include "JtagSC_includes.h"
 
 
//! Module providing TAP requests to JTAG
 
//! Provides a queue of requests to the JTAG interface. Requests are at the
//! level of TAP actions for reset, DR-Scan or IR-Scan.
 
class JtagDriverSC
: public sc_core::sc_module
{
class JtagDriverSC:public sc_core::sc_module {
public:
 
// Constructor
JtagDriverSC (sc_core::sc_module_name name,
sc_core::sc_fifo<TapAction *> *_tapActionQueue);
// Constructor
JtagDriverSC(sc_core::sc_module_name name,
sc_core::sc_fifo < TapAction * >*_tapActionQueue);
 
private:
 
// JTAG instructions
static const uint32_t CHAIN_SELECT_IR = 0x3; //!< Chain Select instruction
static const uint32_t DEBUG_IR = 0x8; //!< Debug instruction
// JTAG instructions
static const uint32_t CHAIN_SELECT_IR = 0x3; //!< Chain Select instruction
static const uint32_t DEBUG_IR = 0x8; //!< Debug instruction
 
// JTAG register lengths (excluding CRC)
static const int JTAG_IR_LEN = 4; //!< JTAG instr reg length
static const int CHAIN_DR_LEN = 4; //!< Length of DR (excl CRC)
static const int RISC_DEBUG_DR_LEN = 65; //!< Length of DR (excl CRC)
static const int REGISTER_DR_LEN = 38; //!< Length of DR (excl CRC)
static const int WISHBONE_DR_LEN = 65; //!< Length of DR (excl CRC)
// JTAG register lengths (excluding CRC)
static const int JTAG_IR_LEN = 4; //!< JTAG instr reg length
static const int CHAIN_DR_LEN = 4; //!< Length of DR (excl CRC)
static const int RISC_DEBUG_DR_LEN = 65; //!< Length of DR (excl CRC)
static const int REGISTER_DR_LEN = 38; //!< Length of DR (excl CRC)
static const int WISHBONE_DR_LEN = 65; //!< Length of DR (excl CRC)
 
// JTAG register address masks
static const uint32_t RISC_DEBUG_ADDR_MASK = 0xffffffff; //!< Mask for addr
static const uint32_t REGISTER_ADDR_MASK = 0x0000001f; //!< Mask for addr
static const uint32_t WISHBONE_ADDR_MASK = 0xffffffff; //!< Mask for addr
// JTAG register address masks
static const uint32_t RISC_DEBUG_ADDR_MASK = 0xffffffff; //!< Mask for addr
static const uint32_t REGISTER_ADDR_MASK = 0x0000001f; //!< Mask for addr
static const uint32_t WISHBONE_ADDR_MASK = 0xffffffff; //!< Mask for addr
 
// JTAG register R/W bit
static const uint64_t RISC_DEBUG_RW = 0x100000000ULL; //!< R/W bit mask
static const uint64_t REGISTER_RW = 0x000000020ULL; //!< R/W bit mask
static const uint64_t WISHBONE_RW = 0x100000000ULL; //!< R/W bit mask
// JTAG register R/W bit
static const uint64_t RISC_DEBUG_RW = 0x100000000ULL; //!< R/W bit mask
static const uint64_t REGISTER_RW = 0x000000020ULL; //!< R/W bit mask
static const uint64_t WISHBONE_RW = 0x100000000ULL; //!< R/W bit mask
 
// JTAG register data field offsets
static const int RISC_DEBUG_DATA_OFF = 33; //!< Offset to data field
static const int REGISTER_DATA_OFF = 6; //!< Offset to data field
static const int WISHBONE_DATA_OFF = 33; //!< Offset to data field
// JTAG register data field offsets
static const int RISC_DEBUG_DATA_OFF = 33; //!< Offset to data field
static const int REGISTER_DATA_OFF = 6; //!< Offset to data field
static const int WISHBONE_DATA_OFF = 33; //!< Offset to data field
 
//! JTAG register data field sizes (all the same)
static const int DR_DATA_LEN = 32;
//! JTAG register data field sizes (all the same)
static const int DR_DATA_LEN = 32;
 
//! CRC length
static const int CRC_LEN = 8;
//! CRC length
static const int CRC_LEN = 8;
 
// OpenRISC 1000 scan chains
static const int OR1K_SC_UNDEF = -1; //!< Undefined OR1K scan chain
static const int OR1K_SC_RISC_DEBUG = 1; //!< for access to SPRs
static const int OR1K_SC_REGISTER = 4; //!< to stall/reset CPU
static const int OR1K_SC_WISHBONE = 5; //!< for memory access
// OpenRISC 1000 scan chains
static const int OR1K_SC_UNDEF = -1; //!< Undefined OR1K scan chain
static const int OR1K_SC_RISC_DEBUG = 1; //!< for access to SPRs
static const int OR1K_SC_REGISTER = 4; //!< to stall/reset CPU
static const int OR1K_SC_WISHBONE = 5; //!< for memory access
 
//! Register addresses for the REGISTER scan chain
static const uint8_t OR1K_RSC_RISCOP = 0x04; //!< Used to reset/stall CPU
//! Register addresses for the REGISTER scan chain
static const uint8_t OR1K_RSC_RISCOP = 0x04; //!< Used to reset/stall CPU
 
// Bits for the RISCOP register
static const uint32_t RISCOP_STALL = 0x00000001; //!< Stall the CPU
static const uint32_t RISCOP_RESET = 0x00000002; //!< Reset the CPU
// Bits for the RISCOP register
static const uint32_t RISCOP_STALL = 0x00000001; //!< Stall the CPU
static const uint32_t RISCOP_RESET = 0x00000002; //!< Reset the CPU
 
//! The JTAG fifo we queue on
sc_core::sc_fifo<TapAction *> *tapActionQueue;
//! The JTAG fifo we queue on
sc_core::sc_fifo < TapAction * >*tapActionQueue;
 
//! The currently selected scan chain
int currentScanChain;
//! The currently selected scan chain
int currentScanChain;
 
// SystemC thread to queue actions
void queueActions ();
// SystemC thread to queue actions
void queueActions();
 
// Or1k JTAG actions
void reset ();
void selectChain (int chain);
uint32_t readReg (uint32_t addr);
uint32_t readReg1 (uint32_t addr,
int bitSizeNoCrc);
uint32_t readReg1 (uint64_t *dRegArray,
uint32_t addr,
int bitSizeNoCrc);
void writeReg (uint32_t addr,
uint32_t data);
// Utilities to compute CRC-8 the OpenRISC way. Versions for "big" and
// "small" numbers.
uint8_t crc8 (uint64_t data,
int size);
uint8_t crc8 (uint64_t *dataArray,
int size);
// Or1k JTAG actions
void reset();
void selectChain(int chain);
uint32_t readReg(uint32_t addr);
uint32_t readReg1(uint32_t addr, int bitSizeNoCrc);
uint32_t readReg1(uint64_t * dRegArray,
uint32_t addr, int bitSizeNoCrc);
void writeReg(uint32_t addr, uint32_t data);
// Utilities to compute CRC-8 the OpenRISC way. Versions for "big" and
// "small" numbers.
uint8_t crc8(uint64_t data, int size);
uint8_t crc8(uint64_t * dataArray, int size);
 
// Utilities to insert and extract bit strings from vectors
void insertBits (uint64_t str,
int strLen,
uint64_t *array,
int startBit);
uint64_t extractBits (uint64_t *array,
int startBit,
int strLen);
// Utilities to insert and extract bit strings from vectors
void insertBits(uint64_t str,
int strLen, uint64_t * array, int startBit);
uint64_t extractBits(uint64_t * array, int startBit, int strLen);
 
}; // JtagDriverSC ()
}; // JtagDriverSC ()
 
#endif // JTAG_DRIVER_SC__H
#endif // JTAG_DRIVER_SC__H
/SprCache.h
31,7 → 31,6
 
#include <stdint.h>
 
 
//-----------------------------------------------------------------------------
//! Module for cacheing SPR accesses by the debug unit
 
52,37 → 51,32
//! forward to the first free slot. This works because there is no function to
//! delete an entry - just to clear the whole table, so holes cannot appear.
//-----------------------------------------------------------------------------
class SprCache
{
class SprCache {
public:
 
// Constructor and destructor
SprCache (int _tableSize = 257);
~SprCache ();
// Constructor and destructor
SprCache(int _tableSize = 257);
~SprCache();
 
// Functions
void clear ();
void write (uint16_t sprNum,
uint32_t value,
bool force);
bool read (uint16_t sprNum,
uint32_t &value);
// Functions
void clear();
void write(uint16_t sprNum, uint32_t value, bool force);
bool read(uint16_t sprNum, uint32_t & value);
 
private:
 
//! The size of the hash table
int tableSize;
//! The size of the hash table
int tableSize;
 
//! Maximum amount of cache left to use, before cacheing is rejected.
int maxToUse;
//! Maximum amount of cache left to use, before cacheing is rejected.
int maxToUse;
 
// The cache, keyed by sprNum. Done as two parallel vectors,
// allowing unambiguous clearing by use of memset for efficiency.
bool *sprIsValid;
uint16_t *sprKeyNum;
uint32_t *sprValue;
// The cache, keyed by sprNum. Done as two parallel vectors,
// allowing unambiguous clearing by use of memset for efficiency.
bool *sprIsValid;
uint16_t *sprKeyNum;
uint32_t *sprValue;
 
}; // SprCache ()
 
}; // SprCache ()
 
#endif // SPR_CACHE__H
#endif // SPR_CACHE__H

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