URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/bench/sysc/include
- from Rev 51 to Rev 52
- ↔ Reverse comparison
Rev 51 → Rev 52
/OrpsocMain.h
55,4 → 55,8
//! CPU clock Half period in timescale units |
#define BENCH_CLK_HALFPERIOD 20 |
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module |
//! Currently is 32MB (8M words) |
#define ORPSOC_SRAM_SIZE (8388608*4) |
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#endif // ORPSOC_MAIN__H |
/Or1200MonitorSC.h
73,7 → 73,11
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// Method to print out the usage for each option |
void printUsage(); |
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// Method to dump simulation's RAM contents at finish |
void memdump(); |
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// The ports |
sc_in<bool> clk; |
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80,6 → 84,7
private: |
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#define DEFAULT_PROF_FILE "sim.profile" |
#define DEFAULT_MEMDUMP_FILE "vorpsoc_ram.dump" |
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// Special NOP instructions |
static const uint32_t NOP_NOP = 0x15000000; //!< Normal nop instruction |
91,10 → 96,14
// Variables for processor status output |
ofstream statusFile; |
ofstream profileFile; |
int profiling_enabled; |
int logging_enabled; |
int exit_perf_summary_enabled; |
int insn_count; |
long long cycle_count; |
ofstream memdumpFile; |
string memdumpFileName; |
int do_memdump, memdump_start_addr, memdump_end_addr; |
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//! Time measurement variable - for calculating performance of the sim |
clock_t start; |
/MemoryLoad.h
47,7 → 47,7
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/* From abstract.h */ |
#define DEFAULT_MEMORY_START 0 |
#define DEFAULT_MEMORY_LEN 0x800000 |
//#define DEFAULT_MEMORY_LEN 0x800000 |
#define STACK_SIZE 20 |
#define LABELNAME_LEN 50 |
#define INSNAME_LEN 15 |