URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/bench/sysc
- from Rev 353 to Rev 354
- ↔ Reverse comparison
Rev 353 → Rev 354
/include/OrpsocMain.h
53,7 → 53,7
#define BENCH_RESET_TIME 10 |
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//! CPU clock Half period in timescale units |
#define BENCH_CLK_HALFPERIOD 20 |
#define BENCH_CLK_HALFPERIOD 10 |
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module |
//! Currently is 32MB (8M words) |
72,7 → 72,7
#define FLASH_END 0xf01fffff |
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//! Default port for RSP to listen on |
#define DEFAULT_RSP_PORT 51000 |
#define DEFAULT_RSP_PORT 50003 |
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//! FIFO size for talking to the RSP connection |
#define RSP_FIFO_SIZE 8 |
/src/OrpsocMain.cpp
349,7 → 349,7
//printf("* Beginning test\n"); |
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// Init the UART function |
uart->initUart(25000000, 115200); |
uart->initUart(50000000, 115200); |
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if (do_program_file_load) // Did the user specify a file to load? |
{ |
/src/Or1200MonitorSC.cpp
188,6 → 188,7
} |
} |
} |
/* |
else if ((strcmp(argv[i], "-u")==0) || |
(strcmp(argv[i], "--bus-log")==0)) |
{ |
213,6 → 214,7
bus_trans_log_start_delay = log_start_time; |
} |
} |
*/ |
} |
} |
|
375,7 → 377,9
printf(" -q, --quiet\t\tDisable the performance summary at end of simulation\n"); |
printf(" -m, --memdump <file> <0xstartaddr> <0xendaddr>\n\t\t\tDump data between <0xstartaddr> and <0xendaddr> from\n\t\t\tthe system's RAM to <file> in binary format on exit\n"); |
printf(" -c, --crash-monitor\tDetect when the processor has crashed and exit\n"); |
/* |
printf(" -u, --bus-log <file> <val>\n\t\t\tLog the wishbone bus transactions to <file>, opt. start\n\t\t\tafter <val> ns\n\n"); |
*/ |
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} |
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