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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/bench/sysc
    from Rev 354 to Rev 362
    ↔ Reverse comparison
  •

Rev 354 → Rev 362

/include/OrpsocAccess.h
43,7 → 43,7
//Old ram_wbclass: class Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000;
class Vorpsoc_top_wb_ram_b3__D20_A19_M800000;
// SoC Arbiter class - will also change if any modifications to bus architecture
class Vorpsoc_top_wb_conbus_top__pi1;
//class Vorpsoc_top_wb_conbus_top__pi1;
 
 
//! Access functions to the Verilator model
/src/OrpsocMain.cpp
69,7 → 69,6
sc_signal<bool> rst;
sc_signal<bool> rstn;
sc_signal<bool> rst_o;
 
sc_signal<bool> jtag_tdi; // JTAG interface
sc_signal<bool> jtag_tdo;
79,18 → 78,6
sc_signal<bool> uart_rx; // External UART
sc_signal<bool> uart_tx;
 
sc_signal<bool> spi_sd_sclk; // SD Card Memory SPI
sc_signal<bool> spi_sd_ss;
sc_signal<bool> spi_sd_miso;
sc_signal<bool> spi_sd_mosi;
sc_signal<uint32_t> gpio_a; // GPIO bus - output only in verilator sims
 
sc_signal<bool> spi1_mosi;
sc_signal<bool> spi1_miso;
sc_signal<bool> spi1_ss;
sc_signal<bool> spi1_sclk;
 
SIM_RUNNING = 0;
 
// Setup the name of the VCD dump file
274,31 → 261,16
// Connect up ORPSoC
orpsoc->clk_pad_i (clk);
orpsoc->rst_pad_i (rstn);
orpsoc->rst_pad_o (rst_o);
orpsoc->rst_n_pad_i (rstn);
 
orpsoc->dbg_tck_pad_i (jtag_tck); // JTAG interface
orpsoc->dbg_tdi_pad_i (jtag_tdi);
orpsoc->dbg_tms_pad_i (jtag_tms);
orpsoc->dbg_tdo_pad_o (jtag_tdo);
orpsoc->tck_pad_i (jtag_tck); // JTAG interface
orpsoc->tdi_pad_i (jtag_tdi);
orpsoc->tms_pad_i (jtag_tms);
orpsoc->tdo_pad_o (jtag_tdo);
 
orpsoc->uart0_srx_pad_i (uart_rx); // External UART
orpsoc->uart0_stx_pad_o (uart_tx);
 
orpsoc->spi_sd_sclk_pad_o (spi_sd_sclk); // SD Card Memory SPI
orpsoc->spi_sd_ss_pad_o (spi_sd_ss);
orpsoc->spi_sd_miso_pad_i (spi_sd_miso);
orpsoc->spi_sd_mosi_pad_o (spi_sd_mosi);
 
orpsoc->spi1_mosi_pad_o (spi1_mosi);
orpsoc->spi1_miso_pad_i (spi1_miso);
orpsoc->spi1_ss_pad_o (spi1_ss);
orpsoc->spi1_sclk_pad_o (spi1_sclk);
 
 
orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in
// verilator sims
 
// Connect up the SystemC modules
reset->clk (clk); // Reset
reset->rst (rst);
321,11 → 293,6
jtag_tdi = 1; // Tie off the JTAG inputs
jtag_tms = 1;
spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
 
spi1_miso = 0;
 
 
if (VCD_enabled)
{
Verilated::traceEverOn (true);
345,7 → 312,7
verilatorVCDFile->open (vcdDumpFile.c_str());
}
}
 
//printf("* Beginning test\n");
 
// Init the UART function
/src/OrpsocAccess.cpp
31,7 → 31,6
 
#include "Vorpsoc_top.h"
#include "Vorpsoc_top_orpsoc_top.h"
#include "Vorpsoc_top_or1k_top.h"
#include "Vorpsoc_top_or1200_top.h"
#include "Vorpsoc_top_or1200_cpu.h"
#include "Vorpsoc_top_or1200_ctrl.h"
58,13 → 57,13
OrpsocAccess::OrpsocAccess (Vorpsoc_top *orpsoc_top)
{
// Assign processor accessor objects
or1200_ctrl = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_ctrl;
or1200_except = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_except;
or1200_sprs = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_sprs;
rf_a = orpsoc_top->v->i_or1k->i_or1200_top->or1200_cpu->or1200_rf->rf_a;
or1200_ctrl = orpsoc_top->v->or1200_top->or1200_cpu->or1200_ctrl;
or1200_except = orpsoc_top->v->or1200_top->or1200_cpu->or1200_except;
or1200_sprs = orpsoc_top->v->or1200_top->or1200_cpu->or1200_sprs;
rf_a = orpsoc_top->v->or1200_top->or1200_cpu->or1200_rf->rf_a;
// Assign main memory accessor objects
// For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0;
ram_wb_sc_sw = orpsoc_top->v->ram_wb0;
ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0;
 
// Assign arbiter accessor object
//wb_arbiter = orpsoc_top->v->wb_conbus;

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