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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/bench/sysc
    from Rev 362 to Rev 363
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  •

Rev 362 → Rev 363

/include/OrpsocAccess.h
41,7 → 41,7
// Main memory access class - will change if main memory size or other
// parameters change
//Old ram_wbclass: class Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000;
class Vorpsoc_top_wb_ram_b3__D20_A19_M800000;
class Vorpsoc_top_wb_ram_b3__D20_A17_M800000;
// SoC Arbiter class - will also change if any modifications to bus architecture
//class Vorpsoc_top_wb_conbus_top__pi1;
 
109,7 → 109,7
Vorpsoc_top_or1200_except *or1200_except;
Vorpsoc_top_or1200_sprs *or1200_sprs;
Vorpsoc_top_or1200_dpram *rf_a;
/*Vorpsoc_top_ram_wb_sc_sw*//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000*/ Vorpsoc_top_wb_ram_b3__D20_A19_M800000 *ram_wb_sc_sw;
/*Vorpsoc_top_ram_wb_sc_sw*//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000*/ Vorpsoc_top_wb_ram_b3__D20_A17_M800000 *ram_wb_sc_sw;
// Arbiter
//Vorpsoc_top_wb_conbus_top__pi1 *wb_arbiter;
 
/src/OrpsocMain.cpp
42,7 → 42,9
 
#include "OrpsocMain.h"
 
#include "JtagSC_includes.h"
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
// them and include/exclude RSP stuff. For now is defined
//#define JTAG_DEBUG
 
#include "Vorpsoc_top.h"
#include "OrpsocAccess.h"
52,7 → 54,12
 
#include "ResetSC.h"
#include "Or1200MonitorSC.h"
#include "GdbServerSC.h"
 
#ifdef JTAG_DEBUG
# include "GdbServerSC.h"
# include "JtagSC_includes.h"
#endif
 
#include "UartSC.h"
 
int SIM_RUNNING;
62,18 → 69,20
sc_set_time_resolution( 1, TIMESCALE_UNIT);
// CPU clock (also used as JTAG TCK) and reset (both active high and low)
sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
sc_clock clk ("clk", clkPeriod);
 
sc_clock clk ("clk", clkPeriod);
sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
sc_signal<bool> rst;
sc_signal<bool> rstn;
 
#ifdef JTAG_DEBUG
sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
 
sc_signal<bool> jtag_tdi; // JTAG interface
sc_signal<bool> jtag_tdo;
sc_signal<bool> jtag_tms;
sc_signal<bool> jtag_trst;
#endif
 
sc_signal<bool> uart_rx; // External UART
sc_signal<bool> uart_tx;
90,17 → 99,21
bool dumping_now = false;
int dump_depth = 99; // Default dump depth
sc_time dump_start,dump_stop, finish_time;
bool finish_time_set = false; // By default we will let the simulation finish naturally
bool finish_time_set = false; // By default we will let the simulation
// finish naturally
VerilatedVcdC *verilatorVCDFile;
/*int*/double time_val;
bool vcd_file_name_given = false;
 
#ifdef JTAG_DEBUG
bool rsp_server_enabled = false;
int rsp_server_port = DEFAULT_RSP_PORT;
#endif
 
// Executable app load variables
int do_program_file_load = 0; // Default: we don't require a file, we use the VMEM
int do_program_file_load = 0; // Default: we don't require a file, we use the
// VMEM
char* program_file; // Old char* style for program name
 
// Verilator accessor
112,9 → 125,14
MemoryLoad *memoryload; // Memory loader
ResetSC *reset; // Generate a RESET signal
 
Or1200MonitorSC *monitor; // Handle l.nop x instructions
 
#ifdef JTAG_DEBUG
JtagSC *jtag; // Generate JTAG signals
GdbServerSC *gdbServer; // Map RSP requests to debug unit
#endif
 
UartSC *uart; // Handle UART signals
 
// Instantiate the Verilator model, VCD trace handler and accessor
129,13 → 147,16
// Instantiate the SystemC modules
reset = new ResetSC ("reset", BENCH_RESET_TIME);
 
#ifdef JTAG_DEBUG
jtag = new JtagSC ("jtag");
#endif
 
uart = new UartSC("uart"); // TODO: Probalby some sort of param
 
// Parse command line options
// Default is for VCD generation OFF, only turned on if specified on command line
// Default is for VCD generation OFF, only turned on if specified on command
// line
// Search through the command line parameters for options
if (argc > 1)
153,7 → 174,8
else if ( (strcmp(argv[i], "-f")==0) ||
(strcmp(argv[i], "--program")==0) )
{
do_program_file_load = 1; // Enable program loading - will be done after sim init
do_program_file_load = 1; // Enable program loading - will be
// done after sim init.
program_file = argv[i+1]; // Old char* style for program name
}
else if ((strcmp(argv[i], "-d")==0) ||
192,6 → 214,7
dump_stop = dump_stop_time;
dump_stop_set = true;
}
#ifdef JTAG_DEBUG
else if ( (strcmp(argv[i], "-r")==0) ||
(strcmp(argv[i], "--rsp")==0) )
{
202,6 → 225,7
i++;
}
}
#endif
/*
Depth setting of VCD doesn't appear to work, I think it's only
configurable during at compile time .
229,8 → 253,10
 
printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
#ifdef JTAG_DEBUG
printf("\nRemote debugging:\n");
printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
#endif
monitor->printUsage();
printf("\n");
return 0;
252,21 → 278,24
cout << ", off at time " << dump_stop.to_string();
cout << endl;
}
#ifdef JTAG_DEBUG
if (rsp_server_enabled)
gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
rsp_server_port, jtag->tapActionQueue);
else
gdbServer = NULL;
#endif
// Connect up ORPSoC
orpsoc->clk_pad_i (clk);
orpsoc->rst_n_pad_i (rstn);
 
#ifdef JTAG_DEBUG
orpsoc->tck_pad_i (jtag_tck); // JTAG interface
orpsoc->tdi_pad_i (jtag_tdi);
orpsoc->tms_pad_i (jtag_tms);
orpsoc->tdo_pad_o (jtag_tdo);
#endif
 
orpsoc->uart0_srx_pad_i (uart_rx); // External UART
orpsoc->uart0_stx_pad_o (uart_tx);
278,6 → 307,7
 
monitor->clk (clk); // Monitor
 
#ifdef JTAG_DEBUG
jtag->sysReset (rst); // JTAG
jtag->tck (jtag_tck);
jtag->tdi (jtag_tdi);
284,6 → 314,7
jtag->tdo (jtag_tdo);
jtag->tms (jtag_tms);
jtag->trst (jtag_trst);
#endif
 
uart->clk (clk); // Uart
uart->uartrx (uart_rx); // orpsoc's receive line
290,8 → 321,10
uart->uarttx (uart_tx); // orpsoc's transmit line
 
// Tie off signals
#ifdef JTAG_DEBUG
jtag_tdi = 1; // Tie off the JTAG inputs
jtag_tms = 1;
#endif
if (VCD_enabled)
{
302,9 → 335,7
// Establish a new trace with its correct time resolution, and trace to
// great depth.
verilatorVCDFile = new VerilatedVcdC ();
//verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
//setSpTimeResolution (sc_get_time_resolution ());
//traceTarget->trace (verilatorVCDFile, 99);
 
orpsoc->trace (verilatorVCDFile, dump_depth);
if (dumping_now)
323,7 → 354,8
cout << "* Loading program from " << program_file << endl;
if (memoryload->loadcode(program_file,0,0) < 0)
{
cout << "* Error: executable file " << program_file << " not loaded" << endl;
cout << "* Error: executable file " << program_file <<
" not loaded" << endl;
}
}
else // Load SRAM from VMEM file
423,8 → 455,9
else
{
// Simple run case
// Ideally a "l.nop 1" will terminate the simulation gracefully
// Need to step at clock period / 4, otherwise model appears to skip the monitor and logging functions sometimes (?!?)
// Ideally a "l.nop 1" will terminate the simulation gracefully.
// Need to step at clock period / 4, otherwise model appears to skip the
// monitor and logging functions sometimes (?!?)
while (SIM_RUNNING)
sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
//sc_start();
432,15 → 465,21
// Free memory
#ifdef JTAG_DEBUG
if (rsp_server_enabled)
delete gdbServer;
 
delete jtag;
#endif
 
delete monitor;
 
delete reset;
 
delete accessor;
 
//delete trace;
 
delete orpsoc;
 
return 0;
/src/OrpsocAccess.cpp
43,7 → 43,7
//#include "Vorpsoc_top_ram_wb__D20_A19_M800000.h"
//#include "Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000.h"
// Include for wb_ram_b3
#include "Vorpsoc_top_wb_ram_b3__D20_A19_M800000.h"
#include "Vorpsoc_top_wb_ram_b3__D20_A17_M800000.h"
// Bus arbiter include - but is for old arbiter, no longer used
//#include "Vorpsoc_top_wb_conbus_top__pi1.h"
 

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