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/eth_stim.v File deleted \ No newline at end of file

/eth_phy_defines.v File deleted

/eth_phy.v File deleted

/clk_gen.v File deleted

clk_gen.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cy7c1354.v =================================================================== --- cy7c1354.v (revision 354) +++ cy7c1354.v (nonexistent) @@ -1,482 +0,0 @@ -//************************************************************************ -//************************************************************************ -//** This model is the property of Cypress Semiconductor Corp and is ** -//** protected by the US copyright laws, any unauthorized copying and ** -//** distribution is prohibited. Cypress reserves the right to change ** -//** any of the functional specifications without any prior notice. ** -//** Cypress is not liable for any damages which may result from the ** -//** use of this functional model. ** -//** ** -//** File Name : CY7C1354B ** -//** ** -//** Revision : 1.1 - 01/30/2004 ** -//** ** -//** The timings are to be selected by the user depending upon the ** -//** frequency of operation from the datasheet. ** -//** ** -//** Model : CY7C1354B - 256K x 36 NoBL Pipelined SRAM ** -//** Queries : MPD Applications ** -//** e-mail: mpd_apps@cypress.com ** -//************************************************************************ -//************************************************************************ - -`timescale 1ns / 10ps - -// NOTE : Any setup/hold errors will force input signal to x state -// or if results indeterminant (write addr) core is reset x - -// define fixed values - -`define wordsize (36 -1) // -`define no_words (262144 -1) // 256K x 36 RAM - -module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); - -inout [`wordsize:0] d; -input clk, // clock input (R) - we_b, // byte write enable(L) - adv_lb, // burst(H)/load(L) address - ce1b, // chip enable(L) - ce2, // chip enable(H) - ce3b, // chip enable(L) - oeb, // async output enable(L)(read) - cenb, // clock enable(L) - mode; // interleave(H)/linear(L) burst -input [3:0] bws; // byte write select(L) -input [18:0] a; // address bus - -// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** -// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** - -//********************************************************************** -// This model is configured for 166 MHz Operation (CY7C1354-166). -//********************************************************************** - `define teohz #3.5 - `define teolz #0 - `define tchz #3.5 - `define tclz #1.5 - - `define tco #3.5 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 - -/********************************************************************** -// Timings for 225MHz -//********************************************************************** - `define teohz #2.8 - `define teolz #0 - `define tchz #2.8 - `define tclz #1.5 - - `define tco #2.8 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 - -//*********************************************************************** -// Timings for 200MHz -//********************************************************************** - `define teohz #3.2 - `define teolz #0 - `define tchz #3.2 - `define tclz #1.5 - - `define tco #3.2 - `define tdoh #1.5 - - `define tas 1.5 - `define tah 0.5 -***********************************************************************/ - -reg notifier; // error support reg's -reg noti1_0; -reg noti1_1; -reg noti1_2; -reg noti1_3; -reg noti1_4; -reg noti1_5; -reg noti1_6; -reg noti2; - - -wire chipen; // combined chip enable (high for an active chip) - -reg chipen_d; // _d = delayed -reg chipen_o; // _o = operational = delayed sig or _d sig - -wire writestate; // holds 1 if any of writebus is low -reg writestate_d; -reg writestate_o; - -wire loadcyc; // holds 1 for load cycles (setup and hold checks) -wire writecyc; // holds 1 for write cycles (setup and hold checks) -wire [3:0] bws; // holds the bws values - -wire [3:0] writebusb; // holds the "internal" bws bus based on we_b -reg [3:0] writebusb_d; -reg [3:0] writebusb_o; - -wire [2:0] operation; // holds chipen, adv_ld and writestate -reg [2:0] operation_d; -reg [2:0] operation_o; - -wire [17:0] a; // address input bus -reg [17:0] a_d; -reg [17:0] a_o; - -reg [`wordsize:0] do; // data output reg -reg [`wordsize:0] di; // data input bus -reg [`wordsize:0] dd; // data delayed bus - -wire tristate; // tristate output (on a bytewise basis) when asserted -reg cetri; // register set by chip disable which sets the tristate -reg oetri; // register set by oe which sets the tristate -reg enable; // register to make the ram enabled when equal to 1 -reg [17:0] addreg; // register to hold the input address -reg [`wordsize:0] pipereg; // register for the output data - -reg [`wordsize:0] mem [0:`no_words]; // RAM array - -reg [`wordsize:0] writeword; // temporary holding register for the write data -reg burstinit; // register to hold a[0] for burst type -reg [18:0] i; // temporary register used to write to all mem locs. -reg writetri; // tristate -reg lw, bw; // pipelined write functions -reg we_bl; - - -wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 36'bz ; // data bus - -assign chipen = (adv_lb == 1 ) ? chipen_d : - ~ce1b & ce2 & ~ce3b ; - -assign writestate = ~& writebusb; - -assign operation = {chipen, adv_lb, writestate}; - -assign writebusb[3:0] = ( we_b ==0 & adv_lb ==0) ? bws[3:0]: - ( we_b ==1 & adv_lb ==0) ? 4'b1111 : - ( we_bl ==0 & adv_lb ==1) ? bws[3:0]: - ( we_bl ==1 & adv_lb ==1) ? 4'b1111 : - 4'bxxxx ; - -assign loadcyc = chipen & !cenb; - -assign writecyc = writestate_d & enable & ~cenb & chipen; // check - -assign tristate = cetri | writetri | oetri; - -pullup (mode); - -// formers for notices/errors etc -// -//$display("NOTICE : xxx :"); -//$display("WARNING : xxx :"); -//$display("ERROR *** : xxx :"); - - -// initialize the output to be tri-state, ram to be disabled - -initial - begin -// signals - - writetri = 0; - cetri = 1; - enable = 0; - lw = 0; - bw = 0; - -// error signals - - notifier = 0; - noti1_0 = 0; - noti1_1 = 0; - noti1_2 = 0; - noti1_3 = 0; - noti1_4 = 0; - noti1_5 = 0; - noti1_6 = 0; - noti2 = 0; - -end - - - -// asynchronous OE - -always @(oeb) -begin - if (oeb == 1) - oetri <= `teohz 1; - else - oetri <= `teolz 0; -end - -// *** SETUP / HOLD VIOLATIONS *** - -always @(noti2) -begin -$display("NOTICE : 020 : Data bus corruption"); - force d =36'bx; - #1; - release d; -end - -always @(noti1_0) -begin -$display("NOTICE : 010 : Byte write corruption"); - force bws = 4'bx; - #1; - release bws; -end - -always @(noti1_1) -begin -$display("NOTICE : 011 : Byte enable corruption"); - force we_b = 1'bx; - #1; - release we_b; -end - -always @(noti1_2) -begin -$display("NOTICE : 012 : CE1B corruption"); - force ce1b =1'bx; - #1; - release ce1b; -end - -always @(noti1_3) -begin -$display("NOTICE : 013 : CE2 corruption"); - force ce2 =1'bx; - #1; - release ce2; -end - -always @(noti1_4) -begin -$display("NOTICE : 014 : CE3B corruption"); - force ce3b =1'bx; - #1; - release ce3b; -end - -always @(noti1_5) -begin -$display("NOTICE : 015 : CENB corruption"); - force cenb =1'bx; - #1; - release cenb; -end - -always @(noti1_6) -begin -$display("NOTICE : 016 : ADV_LB corruption"); - force adv_lb = 1'bx; - #1; - release adv_lb; -end - -// synchronous functions from clk edge - -always @(posedge clk) -if (!cenb) -begin -#0.01; - // latch conditions on adv_lb - - if (adv_lb) - we_bl <= we_bl; - else - we_bl <= we_b; - - chipen_d <= chipen; - - - chipen_o <= chipen; - writestate_o <= writestate; - writestate_d <= writestate_o; - writebusb_o <= writebusb; - writebusb_d <= writebusb_o; - operation_o <= operation; - a_o <= a; - a_d <= a_o; - di = d; - - // execute previously pipelined fns - - if (lw) begin - loadwrite; - lw =0; - end - - if (bw) begin - burstwrite; - bw =0; - end - - // decode input/piplined state - - casex (operation_o) - 3'b0?? : turnoff; - 3'b101 : setlw; - 3'b111 : setbw; - 3'b100 : loadread; - 3'b110 : burstread; - default : unknown; // output unknown values and display an error message - endcase - - do <= `tco pipereg; - -end - -// *** task section *** - -task read; -begin - if (enable) cetri <= `tclz 0; - do <= `tdoh 36'hx; - writetri <= `tchz 0; - pipereg = mem[addreg]; -end -endtask - -task write; -begin - if (enable) cetri <= `tclz 0; - writeword = mem[addreg]; // set up a word to hold the data for the current location - /* overwrite the current word for the bytes being written to */ - if (!writebusb_d[3]) writeword[35:27] = di[35:27]; - if (!writebusb_d[2]) writeword[26:18] = di[26:18]; - if (!writebusb_d[1]) writeword[17:9] = di[17:9]; - if (!writebusb_d[0]) writeword[8:0] = di[8:0]; - writeword = writeword & writeword; //convert z to x states - mem[addreg] = writeword; // store the new word into the memory location - //writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setlw; -begin - lw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task setbw; -begin - bw =1; - writetri <= `tchz 1; // tristate the outputs -end -endtask - -task loadread; -begin - burstinit = a_o[0]; - addreg = a_o; - enable = 1; - read; -end -endtask - -task loadwrite; -begin - burstinit = a_d[0]; - addreg = a_d; - enable = 1; - write; -end -endtask - -task burstread; -begin - burst; - read; -end -endtask - -task burstwrite; -begin - burst; - write; -end -endtask - -task unknown; -begin - do = 36'bx; - // $display ("Unknown function: Operation = %b\n", operation); -end -endtask - -task turnoff; -begin - enable = 0; - cetri <= `tchz 1; - pipereg = 36'h0; -end -endtask - -task burst; -begin - if (burstinit == 0 || mode == 0) - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b01; - 2'b01: addreg[1:0] = 2'b10; - 2'b10: addreg[1:0] = 2'b11; - 2'b11: addreg[1:0] = 2'b00; - default: addreg[1:0] = 2'bxx; - endcase - end - else - begin - case (addreg[1:0]) - 2'b00: addreg[1:0] = 2'b11; - 2'b01: addreg[1:0] = 2'b00; - 2'b10: addreg[1:0] = 2'b01; - 2'b11: addreg[1:0] = 2'b10; - default: addreg[1:0] = 2'bxx; - endcase - end -end -endtask - -// IO checks - -specify -// specify the setup and hold checks - -// notifier will wipe memory as result is indeterminent - -$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); - -// noti1 should make ip = 'bx; - -$setuphold(posedge clk, bws, `tas, `tah, noti1_0); - -$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); -$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); -$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); -$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); - -// noti2 should make d = 36'hxxxxxxxxx; - -$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); -//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2); - -// add extra tests here. - -$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); -$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); - -endspecify - -endmodule - - Index: ddr2_model.v =================================================================== --- ddr2_model.v (revision 354) +++ ddr2_model.v (nonexistent) @@ -1,2024 +0,0 @@ -/**************************************************************************************** -* -* File Name: ddr2.v -* Version: 5.80 -* Model: BUS Functional -* -* Dependencies: ddr2_parameters.vh -* -* Description: Micron SDRAM DDR2 (Double Data Rate 2) -* -* Limitation: - doesn't check for average refresh timings -* - positive ck and ck_n edges are used to form internal clock -* - positive dqs and dqs_n edges are used to latch data -* - test mode is not modeled -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --------------------------------------------------------------------------------------- -* 1.00 JMK 07/29/03 Initial Release -* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH -* 2.20 JMK 08/07/03 General cleanup -* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters. -* Added AL_MIN and AL_MAX parameters. -* Removed support for OCD. -* 2.40 JMK 01/15/04 Removed verilog 2001 constructs. -* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command. -* 2.60 JMK 04/20/04 Fixed tWTR check. -* 2.70 JMK 04/30/04 Added tRFC maximum check. -* Combined Self Refresh and Power Down always blocks. -* Added Reset Function (CKE LOW Anytime). -* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active. -* Added checks for tRAS, tWR, tRTP to any bank during Pre-All. -* tRFC maximum violation will only display one time. -* 2.90 JMK 11/05/04 Fixed DQS checking during write. -* Fixed false tRFC max assertion during power up and self ref. -* Added warning for 200us CKE low time during initialization. -* Added -3, -3E, and -37V speed grades to ddr2_parameters.v -* 3.00 JMK 04/22/05 Removed ODT off requirement during power down. -* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters. -* Added ODT status messages. -* Updated the initialization sequence. -* Disable ODT and CLK pins during self refresh. -* Disable cmd and addr pins during power down and self refresh. -* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks. -* Changed tAXPD message from error to a warning. -* Added tDSS checking. -* Removed tDQSL checking during tWPRE and tWPST. -* Fixed a burst order error during writes. -* Renamed parameters file with .vh extension. -* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ. -* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge. -* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase. -* Clock jitter can be tolerated within specification range. -* Clock frequency is sampled from the CK pin. -* Scaleable up to 64 DQ and 16 DQS bits. -* Read data can be randomly skewed using RANDOM_OUT_DELAY. -* Parameterized read and write DQS, and read DQ. -* Initialization can be bypassed using initialize task. -* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined. -* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined. -* 4.30 JMK 02/15/06 Added dummy write to initialization sequence. -* Removed tWPST maximum checking. -* Rising dqs_n edge latches data when enabled in EMR. -* Fixed a sign error in the tJIT(cc) calculation. -* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined. -* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions. -* Fixed tRCD and tWTR checking. -* Errors entering Power Down or Self Refresh will cause reset. -* Ignore dqs_n when disabled in EMR. -* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh) -* Fixed tRFC max assertion during self refresh. -* Fixed tANPD checking during Power Down. -* Removed dummy write from initialization sequence. -* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh. -* Removed Auto Precharge error message during Power Down Enter. -* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n. -* RDQS can only be enabled in EMR for x8 configurations. -* CAS latency is checked vs frequency when DLL locks. -* tMOD changed from tCK units to ns units. -* Added 50 Ohm setting for Rtt in EMR. -* Improved checking of DQS during writes. -* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16. -* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble. -* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support. -* Added a register delay to ddr2_module.v when RDIMM is defined. -* Added multi-chip package model support in ddr2_mcp.v -* Added High Temp Self Refresh rate setting in EMRS2[7] -* 5.70 JMK 04/23/09 Updated tRPA definition -* Increased internal width to 72 bit DQ bus -* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open) -****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -module ddr2_model ( - ck, - ck_n, - cke, - cs_n, - ras_n, - cas_n, - we_n, - dm_rdqs, - ba, - addr, - dq, - dqs, - dqs_n, - rdqs_n, - odt -); - -`include "ddr2_model_parameters.vh" - - // text macros - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); - if ((1< BL_MAX) - $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); - $timeformat (-12, 1, " ps", 1); - reset_task; - seed = RANDOM_SEED; - ck_cntr = 0; - end - - // calculate the absolute value of a real number - function real abs_value; - input arg; - real arg; - begin - if (arg < 0.0) - abs_value = -1.0 * arg; - else - abs_value = arg; - end - endfunction - -`ifdef MAX_MEM -`else - function get_index; - input [`MAX_BITS-1:0] addr; - begin : index - get_index = 0; - for (memory_index=0; memory_index TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); - if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end - {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task - {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK - {1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && ( - |write_precharge_bank - || (ck_cntr - ck_write_ap < 1) - || (ck_cntr - ck_write < write_latency + burst_length/2 + 2) - || ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end - {1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end - {1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]); - else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end - {1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end - endcase - end - endtask - - task cmd_task; - input cke; - input [2:0] cmd; - input [BA_BITS-1:0] bank; - input [ADDR_BITS-1:0] addr; - reg [`BANKS:0] i; - integer j; - reg [`BANKS:0] tfaw_cntr; - reg [COL_BITS-1:0] col; - begin - - // tRFC max check - if (!er_trfc_max && !in_self_refresh) begin - if ($time - tm_refresh > TRFC_MAX) begin - $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); - er_trfc_max = 1; - end - end - if (cke) begin - if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin - for (j=0; j= BL_MIN) && (burst_length <= BL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end - // Burst Order - burst_order = addr[3]; - if (!burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); - end else if (burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); - end - // CAS Latency - cas_latency = addr[6:4]; - read_latency = cas_latency + additive_latency; - write_latency = read_latency - 1; - if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end - // Test Mode - if (!addr[7]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]); - end - // DLL Reset - dll_reset = addr[8]; - if (!dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); - end else if (dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); - dll_locked = 0; - ck_dll_reset <= ck_cntr; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); - end - // Write Recovery - write_recovery = addr[11:9] + 1; - if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end - // Power Down Mode - low_power = addr[12]; - if (!low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank); - end else if (low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); - end - end - 1 : begin - // DLL Enable - dll_en = !addr[0]; - if (!dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); - end - // Output Drive Strength - if (!addr[1]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank); - end else if (addr[1]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]); - end - // ODT Rtt - odt_rtt = {addr[6], addr[2]}; - if (odt_rtt == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); - odt_en = 0; - end else if (odt_rtt == 2'b01) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else if (odt_rtt == 2'b10) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else if (odt_rtt == 2'b11) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt); - odt_en = 0; - end - // Additive Latency - additive_latency = addr[5:3]; - read_latency = cas_latency + additive_latency; - write_latency = read_latency - 1; - if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); - end - // OCD Program - ocd = addr[9:7]; - if (ocd == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank); - end else if (ocd == 3'b111) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd); - end - - // DQS_N Enable - dqs_n_en = !addr[10]; - if (!dqs_n_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (dqs_n_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en); - end - // RDQS Enable - rdqs_en = addr[11]; - if (!rdqs_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (rdqs_en) begin -`ifdef x8 - if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank); -`else - $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank); - rdqs_en = 0; -`endif - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en); - end - // Output Enable - out_en = !addr[12]; - if (!out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en); - end - end - 2 : begin - // High Temperature Self Refresh rate - if (!addr[7]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Disabled", $time, cmd_string[cmd], bank); - end else if (addr[1]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]); - end - if ((addr & ~(1<<7)) !== 0) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 3 : begin - if (addr !== 0) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - endcase - init_mode_reg[bank] = 1; - ck_load_mode <= ck_cntr; - end - end - REFRESH : begin - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); - er_trfc_max = 0; - ref_cntr = ref_cntr + 1; - tm_refresh <= $time; - end - end - PRECHARGE : begin - if (addr[AP]) begin - // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of - // the number of banks already open or closed. - for (i=0; i<`BANKS; i=i+1) begin - for (j=0; j 3) begin - $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); - end - end - - if (!init_done) begin - $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (active_bank[bank]) begin - $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (addr >= 1<>1) & -1*(1<= 1<>1) & -1*(1<= 1< $time) -// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time); - init_step = init_step + 1; - end - 1 : if (dll_en) init_step = init_step + 1; - 2 : begin - if (&init_mode_reg && dll_reset) begin - active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges - ref_cntr = 0; // require refresh - init_step = init_step + 1; - end - end - 3 : if (ref_cntr == 2) begin - init_step = init_step + 1; - end - 4 : if (!dll_reset) init_step = init_step + 1; - 5 : if (ocd == 3'b111) init_step = init_step + 1; - 6 : begin - if (ocd == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); - init_done = 1; - end - end - endcase - end - end else if (prev_cke) begin - if ((!init_done) && (init_step > 1)) begin - $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end - case (cmd) - REFRESH : begin - for (j=0; j TDQSS*tck_avg)) - $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18); - end - if (check_write_dqs_low[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18); - end - check_write_preamble <= 0; - check_write_postamble <= 0; - check_write_dqs_low <= 0; - end - - if (wr_pipeline[0] || rd_pipeline[0]) begin - bank = ba_pipeline[0]; - row = row_pipeline[0]; - col = col_pipeline[0]; - burst_cntr = 0; - memory_read(bank, row, col, memory_data); - end - - // burst counter - if (burst_cntr < burst_length) begin - burst_position = col ^ burst_cntr; - if (!burst_order) begin - burst_position[BO_BITS-1:0] = col + burst_cntr; - end - burst_cntr = burst_cntr + 1; - end - - // write dqs counter - if (wr_pipeline[WDQS_PRE + 1]) begin - wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1; - end - // write dqs - if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble - check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 1) begin // write data - if ((wdqs_cntr - WDQS_PST)%2) begin - check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; - end else begin - check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; - end - end - if (wdqs_cntr == WDQS_PST) begin // write postamble - check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 0) begin - wdqs_cntr = wdqs_cntr - 1; - end - - // write dq - if (dq_in_valid) begin // write data - bit_mask = 0; - if (diff_ck) begin - for (i=0; i>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - if (burst_cntr%BL_MIN == 0) begin - memory_write(bank, row, col, memory_data); - end - end - if (wr_pipeline[1]) begin - wdq_cntr = burst_length; - end - if (wdq_cntr > 0) begin - wdq_cntr = wdq_cntr - 1; - dq_in_valid = 1'b1; - end else begin - dq_in_valid = 1'b0; - dqs_in_valid <= 1'b0; - for (i=0; i<36; i=i+1) begin - wdqs_pos_cntr[i] <= 0; - end - end - if (wr_pipeline[0]) begin - b2b_write <= 1'b0; - end - if (wr_pipeline[2]) begin - if (dqs_in_valid) begin - b2b_write <= 1'b1; - end - dqs_in_valid <= 1'b1; - end - // read dqs enable counter - if (rd_pipeline[RDQSEN_PRE]) begin - rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1; - end - if (rdqsen_cntr > 0) begin - rdqsen_cntr = rdqsen_cntr - 1; - dqs_out_en = 1'b1; - end else begin - dqs_out_en = 1'b0; - end - - // read dqs counter - if (rd_pipeline[RDQS_PRE]) begin - rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1; - end - // read dqs - if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble - dqs_out = 1'b0; - end else if (rdqs_cntr > RDQS_PST) begin // read data - dqs_out = rdqs_cntr - RDQS_PST; - end else if (rdqs_cntr > 0) begin // read postamble - dqs_out = 1'b0; - end else begin - dqs_out = 1'b1; - end - if (rdqs_cntr > 0) begin - rdqs_cntr = rdqs_cntr - 1; - end - - // read dq enable counter - if (rd_pipeline[RDQEN_PRE]) begin - rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST; - end - if (rdqen_cntr > 0) begin - rdqen_cntr = rdqen_cntr - 1; - dq_out_en = 1'b1; - end else begin - dq_out_en = 1'b0; - end - // read dq - if (rd_pipeline[0]) begin - rdq_cntr = burst_length; - end - if (rdq_cntr > 0) begin // read data - dq_temp = memory_data>>(burst_position*DQ_BITS); - dq_out = dq_temp; - if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - rdq_cntr = rdq_cntr - 1; - end else begin - dq_out = {DQ_BITS{1'b1}}; - end - - // delay signals prior to output - if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin - for (i=0; i dqsck[i] + TQHS + TDQSQ) begin - dqsck_max = dqsck[i] + TQHS + TDQSQ; - end - dqsck_min = -1*TDQSCK; - if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin - dqsck_min = dqsck[i] - TQHS - TDQSQ; - end - - // DQSQ requirements - // 1.) less than tAC - DQSCK - // 2.) less than tDQSQ - // 3.) greater than -tAC - // 4.) greater than tQH from previous DQS edge - dqsq_min = -1*TAC; - if (dqsq_min < dqsck[i] - TQHS) begin - dqsq_min = dqsck[i] - TQHS; - end - if (dqsck_min == dqsck_max) begin - dqsck[i] = dqsck_min; - end else begin - dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); - end - dqsq_max = TAC; - if (dqsq_max > TDQSQ + dqsck[i]) begin - dqsq_max = TDQSQ + dqsck[i]; - end - - dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en; - dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out; - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if (dq_out_en) begin // tLZ2 - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en; - end else begin // tHZ - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en; - end - if (dqsq_min == dqsq_max) begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; - end else begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; - end - end - end - end else begin - out_delay = tck_avg/2.0; - dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; - dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; - dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; - dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; - end - end - endtask - - always @(diff_ck) begin : main - integer i; - - if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) - $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); - data_task; - if (diff_ck) begin - // check setup of command signals - if ($time > TIS) begin - if ($time - tm_cke < TIS) - $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); - if (cke_in) begin - for (i=0; i<22; i=i+1) begin - if ($time - tm_cmd_addr[i] < TIS) - $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); - end - end - end - - // update current state - if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin - // check CL value against the clock frequency - if (cas_latency*tck_avg < CL_TIME) - $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); - // check WR value against the clock frequency - if (write_recovery*tck_avg < TWR) - $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); - dll_locked = 1; - end - if (|auto_precharge_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - // Write with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command - if (write_precharge_bank[i] - && ($time - tm_bank_activate[i] >= TRAS_MIN) - && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin - - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - write_precharge_bank[i] = 0; - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - ck_write_ap = ck_cntr; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - end - // Read with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Additive Latency plus BL/2 cycles after Read command - // 3. tRTP after the last 4-bit prefetch - if (read_precharge_bank[i] - && ($time - tm_bank_activate[i] >= TRAS_MIN) - && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin - - read_precharge_bank[i] = 0; - // In case the internal precharge is pushed out by tRTP, tRP starts at the point where - // the internal precharge happens (not at the next rising clock edge after this event). - if ($time - tm_bank_read_end[i] < TRTP) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); - active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - end - end - end - end - - // respond to incoming command - if (cke_in ^ prev_cke) begin - ck_cke <= ck_cntr; - end - - cmd_task(cke_in, cmd_n_in, ba_in, addr_in); - if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin - al_pipeline[2*additive_latency] = 1'b1; - end - if (al_pipeline[0]) begin - // check tRCD after additive latency - if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin - if (rd_pipeline[2*cas_latency - 1]) begin - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); - end else begin - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); - end - end - // check tWTR after additive latency - if (rd_pipeline[2*cas_latency - 1]) begin - if ($time - tm_write_end < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - end - end - if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin - tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time; - end - for (i=0; i<`BANKS; i=i+1) begin - if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin - tm_bank_write_end[i] <= $time; - tm_write_end <= $time; - end - end - - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - tjit_cc_time = $time - tm_ck_pos - tck_i; - tck_i = $time - tm_ck_pos; - tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tck_avg = tck_avg + tck_i/$itor(TDLLK); - tck_sample[ck_cntr%TDLLK] = tck_i; - tjit_per_rtime = tck_i - tck_avg; - - if (dll_locked) begin - // check accumulated error - terr_nper_rtime = 0; - for (i=0; i<50; i=i+1) begin - terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; - terr_nper_rtime = abs_value(terr_nper_rtime); - case (i) - 0 :; - 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); - 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); - 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); - 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); - 5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER); - default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER); - endcase - end - - // check tCK min/max/jitter - if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) - $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); - if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) - $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); - if (TCK_MIN - tck_avg >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); - if (tck_avg - TCK_MAX >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); - if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) - $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time); - if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) - $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER); - - // check tCL - if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) - $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time); - if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) - $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY); - if (tcl_avg < TCL_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg); - if (tcl_avg > TCL_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg); - end - - // calculate the tch avg jitter - tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tch_avg = tch_avg + tch_i/$itor(TDLLK); - tch_sample[ck_cntr%TDLLK] = tch_i; - - // update timers/counters - tcl_i <= $time - tm_ck_neg; - end - - prev_odt <= odt_in; - // update timers/counters - ck_cntr <= ck_cntr + 1; - tm_ck_pos <= $time; - end else begin - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - if (dll_locked) begin - if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) - $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time); - if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) - $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY); - if (tch_avg < TCH_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg); - if (tch_avg > TCH_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg); - end - - // calculate the tcl avg jitter - tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); - tcl_sample[ck_cntr%TDLLK] = tcl_i; - - // update timers/counters - tch_i <= $time - tm_ck_pos; - end - tm_ck_neg <= $time; - end - - // on die termination - if (odt_en) begin - // clk pin is disabled during self refresh - if (!in_self_refresh && diff_ck) begin - if ($time - tm_odt < TIS) begin - $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); - end - if (prev_odt ^ odt_in) begin - if (!dll_locked) - $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); - if (odt_in && ($time - tm_odt_en < TMOD)) - $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); - if ($time - tm_self_refresh < TXSNR) - $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time); - if (in_self_refresh) - $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); - - // async ODT mode applies: - // 1.) during active power down with slow exit - // 2.) during precharge power down - // 3.) if tANPD has not been satisfied - // 4.) until tAXPD has been satisfied - if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin - if (ck_cntr - ck_slow_exit_pd < TAXPD) - $display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); - if (odt_in) begin - if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1); - odt_state <= #(TAONPD) 1'b1; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0); - odt_state <= #(TAOFPD) 1'b0; - end - // sync ODT mode applies: - // 1.) during normal operation - // 2.) during active power down with fast exit - end else begin - if (odt_in) begin - i = TAOND*2; - odt_pipeline[i] = 1'b1; - end else begin - i = TAOFD*2; - odt_pipeline[i] = 1'b1; - end - end - ck_odt <= ck_cntr; - end - end - if (odt_pipeline[0]) begin - odt_state = ~odt_state; - if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state); - end - end - - // shift pipelines - if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin - al_pipeline = al_pipeline>>1; - wr_pipeline = wr_pipeline>>1; - rd_pipeline = rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - ba_pipeline[i] = ba_pipeline[i+1]; - row_pipeline[i] = row_pipeline[i+1]; - col_pipeline[i] = col_pipeline[i+1]; - end - end - if (|odt_pipeline) begin - odt_pipeline = odt_pipeline>>1; - end - end - - // receiver(s) - task dqs_even_receiver; - input [4:0] i; - reg [71:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - if (rdqs_en) begin // rdqs disables dm - dm_in_pos[i] = 1'b0; - end else begin - dm_in_pos[i] = dm_in[i]; - end - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); - always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); - always @(posedge dqs_even[10]) dqs_even_receiver(10); - always @(posedge dqs_even[11]) dqs_even_receiver(11); - always @(posedge dqs_even[12]) dqs_even_receiver(12); - always @(posedge dqs_even[13]) dqs_even_receiver(13); - always @(posedge dqs_even[14]) dqs_even_receiver(14); - always @(posedge dqs_even[15]) dqs_even_receiver(15); - always @(posedge dqs_even[16]) dqs_even_receiver(16); - always @(posedge dqs_even[17]) dqs_even_receiver(17); - - task dqs_odd_receiver; - input [4:0] i; - reg [71:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - if (rdqs_en) begin // rdqs disables dm - dm_in_neg[i] = 1'b0; - end else begin - dm_in_neg[i] = dm_in[i]; - end - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); - always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); - always @(posedge dqs_odd[10]) dqs_odd_receiver(10); - always @(posedge dqs_odd[11]) dqs_odd_receiver(11); - always @(posedge dqs_odd[12]) dqs_odd_receiver(12); - always @(posedge dqs_odd[13]) dqs_odd_receiver(13); - always @(posedge dqs_odd[14]) dqs_odd_receiver(14); - always @(posedge dqs_odd[15]) dqs_odd_receiver(15); - always @(posedge dqs_odd[16]) dqs_odd_receiver(16); - always @(posedge dqs_odd[17]) dqs_odd_receiver(17); - - // Processes to check hold and pulse width of control signals - always @(cke_in) begin - if ($time > TIH) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); - end - if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time); - tm_cke = $time; - end - always @(odt_in) begin - if (odt_en && !in_self_refresh) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); - if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time); - end - tm_odt = $time; - end - - task cmd_addr_timing_check; - input i; - reg [4:0] i; - begin - if (prev_cke) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time); - end - tm_cmd_addr[i] = $time; - end - endtask - - always @(cs_n_in ) cmd_addr_timing_check( 0); - always @(ras_n_in ) cmd_addr_timing_check( 1); - always @(cas_n_in ) cmd_addr_timing_check( 2); - always @(we_n_in ) cmd_addr_timing_check( 3); - always @(ba_in [ 0]) cmd_addr_timing_check( 4); - always @(ba_in [ 1]) cmd_addr_timing_check( 5); - always @(ba_in [ 2]) cmd_addr_timing_check( 6); - always @(addr_in[ 0]) cmd_addr_timing_check( 7); - always @(addr_in[ 1]) cmd_addr_timing_check( 8); - always @(addr_in[ 2]) cmd_addr_timing_check( 9); - always @(addr_in[ 3]) cmd_addr_timing_check(10); - always @(addr_in[ 4]) cmd_addr_timing_check(11); - always @(addr_in[ 5]) cmd_addr_timing_check(12); - always @(addr_in[ 6]) cmd_addr_timing_check(13); - always @(addr_in[ 7]) cmd_addr_timing_check(14); - always @(addr_in[ 8]) cmd_addr_timing_check(15); - always @(addr_in[ 9]) cmd_addr_timing_check(16); - always @(addr_in[10]) cmd_addr_timing_check(17); - always @(addr_in[11]) cmd_addr_timing_check(18); - always @(addr_in[12]) cmd_addr_timing_check(19); - always @(addr_in[13]) cmd_addr_timing_check(20); - always @(addr_in[14]) cmd_addr_timing_check(21); - always @(addr_in[15]) cmd_addr_timing_check(22); - - // Processes to check setup and hold of data signals - task dm_timing_check; - input i; - reg [4:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); - if (check_dm_tdipw[i]) begin - if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg))) - $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time); - end - end - check_dm_tdipw[i] <= 1'b0; - tm_dm[i] = $time; - end - endtask - - always @(dm_in[ 0]) dm_timing_check( 0); - always @(dm_in[ 1]) dm_timing_check( 1); - always @(dm_in[ 2]) dm_timing_check( 2); - always @(dm_in[ 3]) dm_timing_check( 3); - always @(dm_in[ 4]) dm_timing_check( 4); - always @(dm_in[ 5]) dm_timing_check( 5); - always @(dm_in[ 6]) dm_timing_check( 6); - always @(dm_in[ 7]) dm_timing_check( 7); - always @(dm_in[ 8]) dm_timing_check( 8); - always @(dm_in[ 9]) dm_timing_check( 9); - always @(dm_in[10]) dm_timing_check(10); - always @(dm_in[11]) dm_timing_check(11); - always @(dm_in[12]) dm_timing_check(12); - always @(dm_in[13]) dm_timing_check(13); - always @(dm_in[14]) dm_timing_check(14); - always @(dm_in[15]) dm_timing_check(15); - always @(dm_in[16]) dm_timing_check(16); - always @(dm_in[17]) dm_timing_check(17); - - task dq_timing_check; - input i; - reg [6:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); - if (check_dq_tdipw[i]) begin - if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg))) - $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time); - end - end - check_dq_tdipw[i] <= 1'b0; - tm_dq[i] = $time; - end - endtask - - always @(dq_in[ 0]) dq_timing_check( 0); - always @(dq_in[ 1]) dq_timing_check( 1); - always @(dq_in[ 2]) dq_timing_check( 2); - always @(dq_in[ 3]) dq_timing_check( 3); - always @(dq_in[ 4]) dq_timing_check( 4); - always @(dq_in[ 5]) dq_timing_check( 5); - always @(dq_in[ 6]) dq_timing_check( 6); - always @(dq_in[ 7]) dq_timing_check( 7); - always @(dq_in[ 8]) dq_timing_check( 8); - always @(dq_in[ 9]) dq_timing_check( 9); - always @(dq_in[10]) dq_timing_check(10); - always @(dq_in[11]) dq_timing_check(11); - always @(dq_in[12]) dq_timing_check(12); - always @(dq_in[13]) dq_timing_check(13); - always @(dq_in[14]) dq_timing_check(14); - always @(dq_in[15]) dq_timing_check(15); - always @(dq_in[16]) dq_timing_check(16); - always @(dq_in[17]) dq_timing_check(17); - always @(dq_in[18]) dq_timing_check(18); - always @(dq_in[19]) dq_timing_check(19); - always @(dq_in[20]) dq_timing_check(20); - always @(dq_in[21]) dq_timing_check(21); - always @(dq_in[22]) dq_timing_check(22); - always @(dq_in[23]) dq_timing_check(23); - always @(dq_in[24]) dq_timing_check(24); - always @(dq_in[25]) dq_timing_check(25); - always @(dq_in[26]) dq_timing_check(26); - always @(dq_in[27]) dq_timing_check(27); - always @(dq_in[28]) dq_timing_check(28); - always @(dq_in[29]) dq_timing_check(29); - always @(dq_in[30]) dq_timing_check(30); - always @(dq_in[31]) dq_timing_check(31); - always @(dq_in[32]) dq_timing_check(32); - always @(dq_in[33]) dq_timing_check(33); - always @(dq_in[34]) dq_timing_check(34); - always @(dq_in[35]) dq_timing_check(35); - always @(dq_in[36]) dq_timing_check(36); - always @(dq_in[37]) dq_timing_check(37); - always @(dq_in[38]) dq_timing_check(38); - always @(dq_in[39]) dq_timing_check(39); - always @(dq_in[40]) dq_timing_check(40); - always @(dq_in[41]) dq_timing_check(41); - always @(dq_in[42]) dq_timing_check(42); - always @(dq_in[43]) dq_timing_check(43); - always @(dq_in[44]) dq_timing_check(44); - always @(dq_in[45]) dq_timing_check(45); - always @(dq_in[46]) dq_timing_check(46); - always @(dq_in[47]) dq_timing_check(47); - always @(dq_in[48]) dq_timing_check(48); - always @(dq_in[49]) dq_timing_check(49); - always @(dq_in[50]) dq_timing_check(50); - always @(dq_in[51]) dq_timing_check(51); - always @(dq_in[52]) dq_timing_check(52); - always @(dq_in[53]) dq_timing_check(53); - always @(dq_in[54]) dq_timing_check(54); - always @(dq_in[55]) dq_timing_check(55); - always @(dq_in[56]) dq_timing_check(56); - always @(dq_in[57]) dq_timing_check(57); - always @(dq_in[58]) dq_timing_check(58); - always @(dq_in[59]) dq_timing_check(59); - always @(dq_in[60]) dq_timing_check(60); - always @(dq_in[61]) dq_timing_check(61); - always @(dq_in[62]) dq_timing_check(62); - always @(dq_in[63]) dq_timing_check(63); - always @(dq_in[64]) dq_timing_check(64); - always @(dq_in[65]) dq_timing_check(65); - always @(dq_in[66]) dq_timing_check(66); - always @(dq_in[67]) dq_timing_check(67); - always @(dq_in[68]) dq_timing_check(68); - always @(dq_in[69]) dq_timing_check(69); - always @(dq_in[70]) dq_timing_check(70); - always @(dq_in[71]) dq_timing_check(71); - - task dqs_pos_timing_check; - input i; - reg [5:0] i; - reg [3:0] j; - begin - if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if (check_write_preamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg)) - $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18); - end else if (check_write_postamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) - $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18); - end else begin - if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) - $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18); - end - end - if ($time - tm_dm[i%18] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; - end - end - if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin - wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; - end else begin - wdqs_pos_cntr[i] <= 1; - end - check_dm_tdipw[i%18] <= 1'b1; - check_write_preamble[i] <= 1'b0; - check_write_postamble[i] <= 1'b0; - check_write_dqs_low[i] <= 1'b0; - tm_dqs[i%18] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18); - end - end - tm_dqss_pos[i] <= $time; - tm_dqs_pos[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); - always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); - always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); - always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); - always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); - always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); - always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); - always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); - always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); - always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); - always @(posedge dqs_in[10]) dqs_pos_timing_check(10); - always @(posedge dqs_in[11]) dqs_pos_timing_check(11); - always @(posedge dqs_in[12]) dqs_pos_timing_check(12); - always @(posedge dqs_in[13]) dqs_pos_timing_check(13); - always @(posedge dqs_in[14]) dqs_pos_timing_check(14); - always @(posedge dqs_in[15]) dqs_pos_timing_check(15); - always @(posedge dqs_in[16]) dqs_pos_timing_check(16); - always @(posedge dqs_in[17]) dqs_pos_timing_check(17); - always @(negedge dqs_in[18]) dqs_pos_timing_check(18); - always @(negedge dqs_in[19]) dqs_pos_timing_check(19); - always @(negedge dqs_in[20]) dqs_pos_timing_check(20); - always @(negedge dqs_in[21]) dqs_pos_timing_check(21); - always @(negedge dqs_in[22]) dqs_pos_timing_check(22); - always @(negedge dqs_in[23]) dqs_pos_timing_check(23); - always @(negedge dqs_in[24]) dqs_pos_timing_check(24); - always @(negedge dqs_in[25]) dqs_pos_timing_check(25); - always @(negedge dqs_in[26]) dqs_pos_timing_check(26); - always @(negedge dqs_in[27]) dqs_pos_timing_check(27); - always @(negedge dqs_in[28]) dqs_pos_timing_check(28); - always @(negedge dqs_in[29]) dqs_pos_timing_check(29); - always @(negedge dqs_in[30]) dqs_pos_timing_check(30); - always @(negedge dqs_in[31]) dqs_pos_timing_check(31); - always @(negedge dqs_in[32]) dqs_neg_timing_check(32); - always @(negedge dqs_in[33]) dqs_neg_timing_check(33); - always @(negedge dqs_in[34]) dqs_neg_timing_check(34); - always @(negedge dqs_in[35]) dqs_neg_timing_check(35); - - task dqs_neg_timing_check; - input i; - reg [5:0] i; - reg [3:0] j; - begin - if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18); - if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) - $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18); - end - if ($time - tm_dm[i%18] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; - end - end - check_dm_tdipw[i%18] <= 1'b1; - check_write_dqs_high[i] <= 1'b0; - tm_dqs[i%18] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18); - end - end - tm_dqs_neg[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); - always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); - always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); - always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); - always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); - always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); - always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); - always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); - always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); - always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); - always @(negedge dqs_in[10]) dqs_neg_timing_check(10); - always @(negedge dqs_in[11]) dqs_neg_timing_check(11); - always @(negedge dqs_in[12]) dqs_neg_timing_check(12); - always @(negedge dqs_in[13]) dqs_neg_timing_check(13); - always @(negedge dqs_in[14]) dqs_neg_timing_check(14); - always @(negedge dqs_in[15]) dqs_neg_timing_check(15); - always @(negedge dqs_in[16]) dqs_neg_timing_check(16); - always @(negedge dqs_in[17]) dqs_neg_timing_check(17); - always @(posedge dqs_in[18]) dqs_neg_timing_check(18); - always @(posedge dqs_in[19]) dqs_neg_timing_check(19); - always @(posedge dqs_in[20]) dqs_neg_timing_check(20); - always @(posedge dqs_in[21]) dqs_neg_timing_check(21); - always @(posedge dqs_in[22]) dqs_neg_timing_check(22); - always @(posedge dqs_in[23]) dqs_neg_timing_check(23); - always @(posedge dqs_in[24]) dqs_neg_timing_check(24); - always @(posedge dqs_in[25]) dqs_neg_timing_check(25); - always @(posedge dqs_in[26]) dqs_neg_timing_check(26); - always @(posedge dqs_in[27]) dqs_neg_timing_check(27); - always @(posedge dqs_in[28]) dqs_neg_timing_check(28); - always @(posedge dqs_in[29]) dqs_neg_timing_check(29); - always @(posedge dqs_in[30]) dqs_neg_timing_check(30); - always @(posedge dqs_in[31]) dqs_neg_timing_check(31); - always @(posedge dqs_in[32]) dqs_neg_timing_check(32); - always @(posedge dqs_in[33]) dqs_neg_timing_check(33); - always @(posedge dqs_in[34]) dqs_neg_timing_check(34); - always @(posedge dqs_in[35]) dqs_neg_timing_check(35); - -endmodule Index: orpsoc_testbench.v =================================================================== --- orpsoc_testbench.v (revision 354) +++ orpsoc_testbench.v (revision 360) @@ -1,20 +1,14 @@ ////////////////////////////////////////////////////////////////////// -//// //// -//// ORPSoC Testbench //// -//// //// -//// Description //// -//// ORPSoC Testbench file //// -//// //// -//// To Do: //// -//// //// -//// //// -//// Author(s): //// -//// - jb, jb@orsoc.se //// -//// //// -//// //// +/// //// +/// ORPSoC testbench //// +/// //// +/// Instantiate ORPSoC, monitors, provide stimulus //// +/// //// +/// Julius Baxter, julius@opencores.org //// +/// //// ////////////////////////////////////////////////////////////////////// //// //// -//// Copyright (C) 2009 Authors and OPENCORES.ORG //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// @@ -39,310 +33,191 @@ //// //// ////////////////////////////////////////////////////////////////////// +`include "orpsoc-defines.v" +`include "orpsoc-testbench-defines.v" +`include "test-defines.v" + `include "timescale.v" -`include "orpsoc_testbench_defines.v" -module orpsoc_testbench(); +module orpsoc_testbench; + + reg clk = 0; + reg rst_n = 1; // Active LOW + always + #((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk; - reg clk; - reg rst; - - // Setup global clock. Period defined in orpsoc_testbench_defines.v - initial - begin - clk <= 0; - rst <= 1; - end - - always - begin - #((`CLOCK_PERIOD)/2) clk <= ~clk; - end - - // Assert rst and then bring it low again + // Reset, ACTIVE LOW initial begin - repeat (2) @(negedge clk); - rst <= 0; - repeat (16) @(negedge clk); - rst <= 1; + #1; + repeat (32) @(negedge clk) + rst_n <= 1; + repeat (32) @(negedge clk) + rst_n <= 0; + repeat (32) @(negedge clk) + rst_n <= 1; end +`include "orpsoc-params.v" - // Wires for the dut - wire spi_sd_sclk_o; - wire spi_sd_ss_o; - wire spi_sd_miso_i; - wire spi_sd_mosi_o; -`ifdef USE_SDRAM - wire [15:0] mem_dat_io; - wire [12:0] mem_adr_o; - wire [1:0] mem_dqm_o; - wire [1:0] mem_ba_o; - wire mem_cs_o; - wire mem_ras_o; - wire mem_cas_o; - wire mem_we_o; - wire mem_cke_o; - wire spi_flash_sclk_o; - wire spi_flash_ss_o; - wire spi_flash_miso_i; - wire spi_flash_mosi_o; - wire spi_flash_w_n_o; - wire spi_flash_hold_n_o; -`endif // `ifdef USE_SDRAM - -`ifdef USE_ETHERNET - wire [1:1] eth_sync_o; - wire [1:1] eth_tx_o; - wire [1:1] eth_rx_i; - wire eth_clk_i; - wire [1:1] eth_md_io; - wire [1:1] eth_mdc_o; +`ifdef JTAG_DEBUG + wire tdo_pad_o; + wire tck_pad_i; + wire tms_pad_i; + wire tdi_pad_i; +`endif +`ifdef UART0 + wire uart0_stx_pad_o; + wire uart0_srx_pad_i; `endif - wire spi1_mosi_o; - wire spi1_miso_i; - wire spi1_ss_o; - wire spi1_sclk_o; - wire [8-1:0] gpio_a_io; - wire uart0_srx_i; - wire uart0_stx_o; - wire dbg_tdi_i; - wire dbg_tck_i; - wire dbg_tms_i; - wire dbg_tdo_o; - wire rst_i; - wire rst_o; - wire clk_i; + orpsoc_top dut + ( + .clk_pad_i (clk), +`ifdef JTAG_DEBUG + .tms_pad_i (tms_pad_i), + .tck_pad_i (tck_pad_i), + .tdi_pad_i (tdi_pad_i), + .tdo_pad_o (tdo_pad_o), +`endif +`ifdef UART0 + .uart0_stx_pad_o (uart0_stx_pad_o), + .uart0_srx_pad_i (uart0_srx_pad_i), +`endif + .rst_n_pad_i (rst_n) + ); + // + // Instantiate OR1200 monitor + // + or1200_monitor monitor(); - assign clk_i = clk; - assign rst_i = rst; +`ifndef SIM_QUIET + `define CPU_ic_top or1200_ic_top + `define CPU_dc_top or1200_dc_top + wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en; + always @(posedge ic_en) + $display("Or1200 IC enabled at %t", $time); - // Tie off some inputs - assign spi1_miso_i = 0; - assign uart0_srx_i = 1; + wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en; + always @(posedge dc_en) + $display("Or1200 DC enabled at %t", $time); +`endif - orpsoc_top dut - ( - // Outputs - .spi_sd_sclk_pad_o (spi_sd_sclk_o), - .spi_sd_ss_pad_o (spi_sd_ss_o), - .spi_sd_mosi_pad_o (spi_sd_mosi_o), - .spi1_mosi_pad_o (spi1_mosi_o), - .spi1_ss_pad_o (spi1_ss_o), - .spi1_sclk_pad_o (spi1_sclk_o), - .uart0_stx_pad_o (uart0_stx_o), - .dbg_tdo_pad_o (dbg_tdo_o), - .rst_pad_o (rst_o), - .gpio_a_pad_io (gpio_a_io[8-1:0]), - // Inputs - .spi_sd_miso_pad_i (spi_sd_miso_i), - .spi1_miso_pad_i (spi1_miso_i), - .uart0_srx_pad_i (uart0_srx_i), - .dbg_tdi_pad_i (dbg_tdi_i), - .dbg_tck_pad_i (dbg_tck_i), - .dbg_tms_pad_i (dbg_tms_i), -`ifdef USE_ETHERNET - // Ethernet ports - .eth_md_pad_io (eth_md_io[1:1]), - .eth_mdc_pad_o (eth_mdc_o[1:1]), - .eth_sync_pad_o (eth_sync_o[1:1]), - .eth_tx_pad_o (eth_tx_o[1:1]), - .eth_rx_pad_i (eth_rx_i[1:1]), - .eth_clk_pad_i (eth_clk_i), -`endif // `ifdef USE_ETHERNET - // SDRAM and flash memory ports -`ifdef USE_SDRAM - .mem_dat_pad_io (mem_dat_io[15:0]), - .mem_adr_pad_o (mem_adr_o[12:0]), - .mem_dqm_pad_o (mem_dqm_o[1:0]), - .mem_ba_pad_o (mem_ba_o[1:0]), - .mem_cs_pad_o (mem_cs_o), - .mem_ras_pad_o (mem_ras_o), - .mem_cas_pad_o (mem_cas_o), - .mem_we_pad_o (mem_we_o), - .mem_cke_pad_o (mem_cke_o), - .spi_flash_sclk_pad_o (spi_flash_sclk_o), - .spi_flash_ss_pad_o (spi_flash_ss_o), - .spi_flash_mosi_pad_o (spi_flash_mosi_o), - .spi_flash_w_n_pad_o (spi_flash_w_n_o), - .spi_flash_hold_n_pad_o (spi_flash_hold_n_o), - .spi_flash_miso_pad_i (spi_flash_miso_i), -`endif - .rst_pad_i (rst_i), - .clk_pad_i (clk_i)); - -`ifdef VPI_DEBUG_ENABLE +`ifdef JTAG_DEBUG + `ifdef VPI_DEBUG // Debugging interface - vpi_debug_module vpi_dbg( - .tms(dbg_tms_i), - .tck(dbg_tck_i), - .tdi(dbg_tdi_i), - .tdo(dbg_tdo_o)); -`else - // If no VPI debugging, tie off JTAG inputs - assign dbg_tdi_i = 1; - assign dbg_tck_i = 0; - assign dbg_tms_i = 1; -`endif - - - - // External memories, if enabled -`ifdef USE_SDRAM - // SPI Flash - AT26DFxxx spi_flash + vpi_debug_module vpi_dbg ( - // Outputs - .SO (spi_flash_miso_i), - // Inputs - .CSB (spi_flash_ss_o), - .SCK (spi_flash_sclk_o), - .SI (spi_flash_mosi_o), - .WPB (spi_flash_w_n_o) - //.HOLDB (spi_flash_hold_n_o) + .tms(tms_pad_i), + .tck(tck_pad_i), + .tdi(tdi_pad_i), + .tdo(tdo_pad_o) ); - - // SDRAM - mt48lc16m16a2 sdram - ( - // Inouts - .Dq (mem_dat_io), - // Inputs - .Addr (mem_adr_o), - .Ba (mem_ba_o), - .Clk (clk_i), - .Cke (mem_cke_o), - .Cs_n (mem_cs_o), - .Ras_n (mem_ras_o), - .Cas_n (mem_cas_o), - .We_n (mem_we_o), - .Dqm (mem_dqm_o)); - -`endif // !`ifdef USE_SDRAM - -`ifdef USE_ETHERNET - - reg eth_clk; - initial - eth_clk <= 0; - - always - #(8/2) eth_clk <= ~eth_clk; // 125 Mhz clock - - assign eth_clk_i = eth_clk; + `else + // If no VPI debugging, tie off JTAG inputs + assign tdi_pad_i = 1; + assign tck_pad_i = 0; + assign tms_pad_i = 1; + `endif // !`ifdef VPI_DEBUG_ENABLE +`endif // `ifdef JTAG_DEBUG - - - wire [3:0] ethphy_mii_tx_d; - wire ethphy_mii_tx_en; - wire ethphy_mii_tx_err; - wire mcoll_o; - wire mcrs_o; - wire md_io; - wire mrx_clk_o; - wire [3:0] mrxd_o; - wire mrxdv_o; - wire mrxerr_o; - wire mtx_clk_o; - wire smii_rx; - wire fast_ethernet, duplex, link; - /* Converts SMII back to MII */ - smii_phy smii_phyend - ( - // Outputs - .smii_rx (eth_rx_i[1:1]), /* SMII RX */ - .ethphy_mii_tx_d (ethphy_mii_tx_d[3:0]), /* MII TX */ - .ethphy_mii_tx_en (ethphy_mii_tx_en), /* MII TX */ - .ethphy_mii_tx_err (ethphy_mii_tx_err), /* MII TX */ - // Inputs - .smii_tx (eth_tx_o[1:1]), /* SMII TX */ - .smii_sync (eth_sync_o[1:1]), /* SMII SYNC */ - .ethphy_mii_tx_clk (mtx_clk_o), /* MII TX */ + initial + begin +`ifndef SIM_QUIET + $display("\n* Starting simulation of design RTL.\n* Test: %s\n", + `TEST_NAME_STRING ); +`endif - .ethphy_mii_rx_d (mrxd_o[3:0]), /* MII RX */ - .ethphy_mii_rx_dv (mrxdv_o), /* MII RX */ - .ethphy_mii_rx_err (mrxerr_o), /* MII RX */ - .ethphy_mii_rx_clk (mrx_clk_o), /* MII RX */ - - .ethphy_mii_mcoll (), - .ethphy_mii_crs (mcrs_o), - .fast_ethernet (fast_ethernet), - .duplex (duplex), - .link (link), - .clk (eth_clk_i), - .rst_n (rst_i)); +`ifdef VCD + `ifdef VCD_DELAY + #(`VCD_DELAY); + `endif -`ifdef ENABLE_ETH_STIM - /* Generates an RX packet */ - `include "eth_stim.v" + // Delay by x insns + `ifdef VCD_DELAY_INSNS + #10; // Delay until after the value becomes valid + while (monitor.insns < `VCD_DELAY_INSNS) + @(posedge clk); + `endif + + `ifdef SIMULATOR_MODELSIM + // Modelsim can GZip VCDs on the fly if given in the suffix + `define VCD_SUFFIX ".vcd.gz" + `else + `define VCD_SUFFIX ".vcd" + `endif + +`ifndef SIM_QUIET + $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX}); +`endif + $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX}); + `ifndef VCD_DEPTH + `define VCD_DEPTH 0 + `endif + $dumpvars(`VCD_DEPTH); `endif - - eth_phy eth_phy0 - ( - // Outputs - .mtx_clk_o (mtx_clk_o), - .mrx_clk_o (mrx_clk_o), - .mrxd_o (mrxd_o[3:0]), - .mrxdv_o (mrxdv_o), - .mrxerr_o (mrxerr_o), - .mcoll_o (mcoll_o), - .mcrs_o (mcrs_o), - // Sideband outputs for smii converter --jb - .link_o (link), - .speed_o (fast_ethernet), - .duplex_o (duplex), - // Inouts - .md_io (eth_md_io[1:1]), - // Inputs - .m_rst_n_i (rst_i), - .mtxd_i (ethphy_mii_tx_d[3:0]), - .mtxen_i (ethphy_mii_tx_en), - .mtxerr_i (ethphy_mii_tx_err), - .mdc_i (eth_mdc_o[1:1])); + + end // initial begin -`endif // `ifdef USE_ETHERNET - - -initial - begin - $display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING); -`ifdef USE_SDRAM - $display("Using SDRAM - loading application from SPI flash memory\n"); +`ifdef END_TIME + initial begin + #(`END_TIME); +`ifndef SIM_QUIET + $display("* Finish simulation due to END_TIME being set at %t", $time); +`endif + $finish; + end `endif -`ifdef VCD - $display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"}); - $dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"}); - $dumpvars(0); -`endif - end - - // Instantiate the monitor - or1200_monitor monitor(); - - // If we're using UART for printf output, include the - // UART decoder -`ifdef UART_PRINTF +`ifdef END_INSNS + initial begin + #10 + while (monitor.insns < `END_INSNS) + @(posedge clk); + `ifndef SIM_QUIET + $display("* Finish simulation due to END_INSNS count (%d) reached at %t", + `END_INSNS, $time); + `endif + $finish; + end +`endif + +`ifdef UART0 + // + // UART0 decoder + // uart_decoder #( - .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS - ) + .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS + ) uart0_decoder ( .clk(clk), - .uart_tx(uart0_stx_o) + .uart_tx(uart0_stx_pad_o) ); -`endif + // UART0 stimulus + uart_stim + #( + .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS + ) + uart0_stim + ( + .clk(clk), + .uart_rx(uart0_srx_pad_i) + ); + +`endif // `ifdef UART0 + endmodule // orpsoc_testbench // Local Variables: -// verilog-library-files:("../../rtl/verilog/orpsoc_top.v") -// verilog-library-directories:("." "../../rtl/verilog") +// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top") +// verilog-library-files:() +// verilog-library-extensions:(".v" ".h") // End: +

/or1200_monitor.v