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    /openrisc/trunk/orpsocv2/bench/verilog
    from Rev 397 to Rev 403
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  •

Rev 397 → Rev 403

/timescale.v File deleted
/orpsoc-testbench-defines.v File deleted
/AT26DFxxx.v
89,7 → 89,8
parameter DEVICE = "AT25DF041A"; // Device selected
parameter PRELOAD = 1; // preload memory with content in MEMORY_FILE
parameter MEMORY_FILE = "flash.in"; // Memory pre-load
 
parameter VERBOSE = 1;
// ********************************************************************* //
//Timing Parameters :
// ******************************************************************** //
584,8 → 585,9
#tV SO_reg = temp_data[i];
SO_on = 1'b1;
if (i == 0)
begin
//$display ("Data: %h read from memory location %h",temp_data,read_addr);
begin
if (VERBOSE)
$display ("Data: %h read from memory location %h",temp_data,read_addr);
read_addr = read_addr + 1; // next byte
i = 7;
if (read_addr >= (MEMSIZE-1))
/include/orpsoc-testbench-defines.v
0,0 → 1,2
 
 
/include/timescale.v
0,0 → 1,41
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench Timescale ////
//// ////
//// Description ////
//// ORPSoC testbench timescale file ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
/smii_phy.v
96,22 → 96,14
 
always @(posedge clk)
begin
if (!rst_n)
begin
state_shiftreg <= 10'b0000000001;
end
if (smii_sync) /* sync signal from MAC */
state_shiftreg <= 10'b0000000010;
else if (state_shiftreg[10])
state_shiftreg <= 10'b0000000001;
else
begin
if (smii_sync) /* sync signal from MAC */
state_shiftreg <= 10'b0000000010;
else if (state_shiftreg[10])
state_shiftreg <= 10'b0000000001;
else
state_shiftreg[10:2] <= state_shiftreg[9:1];
end // else: !if(!rst_n)
end // always @ (posedge clk)
state_shiftreg[10:2] <= state_shiftreg[9:1];
end
 
/* counter from 0 to 9, counting the 10-bit segments we'll transmit
via SMII*/
reg [3:0] segment_ctr;
138,7 → 130,6
/* RX path logic PHY->(MII->SMII)->MAC */
/**************************************************************************/
 
reg rx_nibble_sel, rx_byte_valid;
reg [7:0] rx_data_byte_rx_clk;
 
reg [4:0] rx_dv_nib_0;
147,14 → 138,12
 
// Allow us to check if RX DV has been low for a while
reg [3:0] rx_dv_long_low_sr;
wire rx_dv_long_low;
wire dv_long_low;
always @(posedge ethphy_mii_rx_clk)
rx_dv_long_low_sr[3:0] <= {rx_dv_long_low_sr[2:0], ethphy_mii_rx_dv};
assign rx_dv_long_low = ~(|rx_dv_long_low_sr[3:0]);
reg rx_dv;
wire [8:0] rx_fifo_out;
assign rx_dv_long_low = ~(|rx_dv_long_low_sr);
wire [9:0] rx_fifo_out;
wire rx_fifo_empty,rx_fifo_almost_empty;
reg rx_fifo_pop;
always @(posedge ethphy_mii_rx_clk or negedge rst_n)
begin
176,34 → 165,75
end
end // always @ (posedge ethphy_mii_rx_clk or negedge rst_n)
 
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) rx_fifo_pop <= 0;
else rx_fifo_pop <= (rx_fifo_almost_empty) ? (rx_fifo_pop ? ~rx_fifo_empty : rx_fifo_pop) : 1;
wire rx_fifo_pop;
reg ethphy_mii_rx_dv_r;
wire ethphy_mii_rx_dv_re;
wire ethphy_mii_rx_dv_fe;
always @(posedge ethphy_mii_rx_clk)
ethphy_mii_rx_dv_r <= ethphy_mii_rx_dv;
 
rx_dv <= (state_shiftreg[10] & (((rx_segment_begin_num == (segment_ctr-1)) && !fast_ethernet)| fast_ethernet)) ? (rx_fifo_pop) : rx_dv;
end
assign ethphy_mii_rx_dv_re = ethphy_mii_rx_dv & !ethphy_mii_rx_dv_r;
assign ethphy_mii_rx_dv_fe = !ethphy_mii_rx_dv & ethphy_mii_rx_dv_r;
reg rx_fifo_final_pop;
 
always @(posedge clk)
begin
/* remember which counter value we were at when rx enable/valid
went high.
This is only useful when not doing fast ethernet*/
if (!rst_n)
rx_fifo_final_pop <= 0;
else if (rx_fifo_final_pop & state_shiftreg[1] &
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet))
rx_fifo_final_pop <= 0;
else if (rx_fifo_pop & rx_fifo_empty)
rx_fifo_final_pop <= 1;
always @(posedge ethphy_mii_rx_clk)
if (ethphy_mii_rx_dv_re)
rx_segment_begin_num <= segment_ctr;
 
/* rx en has gone high - remember the sequence number we're in */
if ((rx_segment_begin_num == 4'hf) & (~rx_dv_long_low))
rx_segment_begin_num <= segment_ctr;
/* If rx enable goes low again, reset the segment number */
if (rx_dv_long_low)
/* reset to 0xf */
rx_segment_begin_num <= 4'hf;
end
reg do_fifo_pop;
always @(posedge clk)
if (!rst_n)
do_fifo_pop <= 0;
else if (rx_fifo_empty)
do_fifo_pop <= 0;
else if (!rx_fifo_almost_empty)
do_fifo_pop <= 1;
assign rx_fifo_pop = (state_shiftreg[9] & do_fifo_pop) &
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet)
| fast_ethernet);
 
reg rx_dv_r;
wire rx_dv;
// Error where rx_dv goes high one cycle too late, so is low for very first data frame - FIXME!
//reg rx_dv;
always @(posedge clk)
if (!rst_n)
rx_dv_r <= 0;
else if (rx_fifo_final_pop & state_shiftreg[1] &
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet))
rx_dv_r <= 0;
else if (rx_fifo_pop)
rx_dv_r <= rx_fifo_out[9];
 
assign rx_dv = rx_dv_r | rx_fifo_pop;
 
reg sending_segment;
always @(posedge clk)
if (!rst_n)
sending_segment <= 0;
else if (rx_fifo_final_pop & state_shiftreg[1] & (((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet))
sending_segment <= 0;
else if ((state_shiftreg[9] & do_fifo_pop) & (((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet))
sending_segment <= !rx_fifo_empty;
/* A fifo, storing RX bytes coming from the PHY interface */
generic_fifo #(9, 64) rx_fifo
generic_fifo #(10, 1024, 10) rx_fifo
(
// Outputs
.psh_full (),
214,46 → 244,61
.async_rst_n (rst_n),
.psh_clk (ethphy_mii_rx_clk),
.psh_we (rx_nib_first_r),
.psh_d ({ethphy_mii_rx_err,ethphy_mii_rx_d,rx_dv_nib_0[3:0]}),
.psh_d ({ethphy_mii_rx_dv,ethphy_mii_rx_err,ethphy_mii_rx_d,rx_dv_nib_0[3:0]}),
.pop_clk (clk),
.pop_re ((state_shiftreg[1] & rx_fifo_pop)&(((rx_segment_begin_num == segment_ctr) && !fast_ethernet)| fast_ethernet)));
.pop_re (rx_fifo_pop)
);
 
`ifdef RX_SYNC_1
/* Assign the rx line out */
reg [9:0] smii_rx_frame_next;
always @(posedge clk)
smii_rx <= state_shiftreg[1] ? ethphy_mii_crs : /* 1st bit is MII CRS */
state_shiftreg[2] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) |
rx_dv) :
// inter-frame status byte or data byte
state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) :
state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) :
state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[2]) : duplex) :
state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[3]) : link) :
state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[4]) : jabber) :
state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[5]) : 1) :
state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[6]) : 0) :
state_shiftreg[10] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0;
if (state_shiftreg[10])
smii_rx_frame_next <= rx_dv ? {rx_fifo_out[7:0],1'b1,ethphy_mii_crs} :
{3'b101,jabber,link,duplex,fast_ethernet,
ethphy_mii_rx_err,1'b0,ethphy_mii_crs};
 
`else // !`ifdef RX_SYNC_1
/* Assign the rx line out */
always @(posedge clk)
smii_rx <= state_shiftreg[10] ? ethphy_mii_crs : /* 1st bit is MII CRS */
state_shiftreg[1] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) |
rx_dv) :
// inter-frame status byte or data byte
state_shiftreg[2] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) :
state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) :
state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[2]) : duplex) :
state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[3]) : link) :
state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[4]) : jabber) :
state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[5]) : 1) :
state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[6]) : 0) :
state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0;
`endif // !`ifdef RX_SYNC_1
smii_rx <= state_shiftreg[10] & smii_rx_frame_next[0] |
state_shiftreg[1] & smii_rx_frame_next[1] |
state_shiftreg[2] & smii_rx_frame_next[2] |
state_shiftreg[3] & smii_rx_frame_next[3] |
state_shiftreg[4] & smii_rx_frame_next[4] |
state_shiftreg[5] & smii_rx_frame_next[5] |
state_shiftreg[6] & smii_rx_frame_next[6] |
state_shiftreg[7] & smii_rx_frame_next[7] |
state_shiftreg[8] & smii_rx_frame_next[8] |
state_shiftreg[9] & smii_rx_frame_next[9];
reg [79:0] rx_statename;
always @* begin
case (1)
state_shiftreg[1] :
rx_statename = "CRS";
state_shiftreg[2] :
rx_statename = "RX_DV";
state_shiftreg[3]:
rx_statename = "RXD0/RXERR";
state_shiftreg[4]:
rx_statename = "RXD1/Fast";
state_shiftreg[5]:
rx_statename = "RXD2/Dupl";
state_shiftreg[6]:
rx_statename = "RXD3/Link";
state_shiftreg[7]:
rx_statename = "RXD4/Jabb";
state_shiftreg[8]:
rx_statename = "RXD5/UNV";
state_shiftreg[9]:
rx_statename = "RXD6/FCD";
state_shiftreg[10] :
rx_statename = "RXD7/AS1";
default:
rx_statename = "XXXXXXX";
endcase // case (1)
end // always @ *
 
/* Status seq.: CRS, DV, ER, Speed, Duplex, Link, Jabber, UPV, FCD, 1 */
// {1'b1,1'b0,1'b1,jabber,link,duplex,,ethphy_mii_rx_err});
402,18 → 447,18
else /* Finish up */
begin
tx_byte_to_phy <= 3;
ethphy_mii_tx_en <= 0;
end
end
else if (tx_byte_to_phy == 3) /* De-assert TX_EN */
begin
tx_byte_to_phy <= 2'b00;
ethphy_mii_tx_en <= 0;
end
end // else: !if(!rst_n)
end // always @ (posedge ethphy_mii_tx_clk or negedge rst_n)
 
/* A fifo, storing TX bytes coming from the SMII interface */
generic_fifo #(9, 64) tx_fifo
generic_fifo #(9, 64, 6) tx_fifo
(
// Outputs
.psh_full (tx_fifo_full),
458,17 → 503,24
output reg [dw-1:0] pop_q;
output pop_empty;
output wire almost_empty;
 
integer i;
/* Actual FIFO memory */
reg [dw-1:0] fifo_mem [0:size-1];
 
initial
begin
for (i=0;i<size;i=i+1)
begin
fifo_mem[i] = {dw{1'b0}};
end
end
 
/* FIFO position ptr regs */
reg [size_log_2 - 1 : 0 ] wr_ptr, rd_ptr, ctr;
 
integer i;
 
/* FIFO full signal for push side */
//assign psh_full = (ptr == size-1) ? 1 : 0;
480,17 → 532,24
//assign pop_empty = ctr==0;
assign pop_empty = rd_ptr == wr_ptr;
 
assign almost_empty = ctr < 2;
assign almost_empty = ctr < 16;
always @(posedge pop_re or negedge async_rst_n)
begin
if (!async_rst_n)
rd_ptr <= 0;
begin
rd_ptr <= 0;
pop_q <= 0;
end
else
begin
pop_q = fifo_mem[rd_ptr];
rd_ptr <= rd_ptr + 1;
ctr <= ctr - 1;
if (!pop_empty)
begin
pop_q <= fifo_mem[rd_ptr];
ctr <= ctr - 1;
rd_ptr <= rd_ptr + 1;
end
end
end
 
512,5 → 571,3
endmodule // generic_fifo
 
/orpsoc_testbench.v
45,7 → 45,7
reg rst_n = 1; // Active LOW
always
#((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk;
#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
// Reset, ACTIVE LOW
initial
96,11 → 96,11
`ifndef SIM_QUIET
`define CPU_ic_top or1200_ic_top
`define CPU_dc_top or1200_dc_top
wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en;
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
always @(posedge ic_en)
$display("Or1200 IC enabled at %t", $time);
 
wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en;
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
always @(posedge dc_en)
$display("Or1200 DC enabled at %t", $time);
`endif
128,7 → 128,7
initial
begin
`ifndef SIM_QUIET
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
$display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`endif
/mt48lc16m16a2.v
38,16 → 38,45
**************************************************************************/
 
`include "timescale.v"
`include "test-defines.v"
 
// Uncomment one of the following to have the appropriate size definitions
// for the part.
//`define MT48LC32M16 // 64MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
 
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
 
parameter addr_bits = 13;
parameter data_bits = 16;
parameter col_bits = 9;
parameter mem_sizes = 4194303;
 
`ifdef MT48LC32M16
// Params. for mt48lc32m16a2 (64MB part)
parameter addr_bits = 13;
parameter col_bits = 10;
parameter mem_sizes = 8388606;
`endif
 
`ifdef MT48LC16M16
// Params. for mt48lc16m16a2 (32MB part)
parameter addr_bits = 13;
parameter col_bits = 9;
parameter mem_sizes = 4194303;
`endif
`ifdef MT48LC4M16
//Params for mt48lc4m16a2 (8MB part)
parameter addr_bits = 12;
parameter col_bits = 8;
parameter mem_sizes = 1048575;
`endif
// Common to all parts
parameter data_bits = 16;
 
 
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
61,7 → 90,7
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
 
reg [31 : 0] Bank0_32bit [0 : (mem_sizes/2)]; // Temporary 32-bit wide array to hold readmemh()'d data before loading into 16-bit wide array
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
157,6 → 186,9
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
 
integer mem_cnt;
 
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
171,8 → 203,32
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
//`define INIT_CLEAR_MEM_BANKS
`ifdef INIT_CLEAR_MEM_BANKS // Added, jb
// Initialse the memory before we use it, clearing x's
for(mem_cnt = 0; mem_cnt < mem_sizes; mem_cnt = mem_cnt + 1)
begin
Bank0[mem_cnt] = 0;
Bank1[mem_cnt] = 0;
Bank2[mem_cnt] = 0;
Bank3[mem_cnt] = 0;
end
`endif
 
`ifdef PRELOAD_RAM // Added jb
$display("* Preloading SDRAM bank 0.\n");
// Uses the vmem file for the internal SRAM, so words are 32-bits wide
// and we need to copy them into the 16-bit wide array, which the simulator
// can't figure out how to do, so we'll do it manually here.
$readmemh("sram.vmem", Bank0_32bit);
for (mem_cnt=0;mem_cnt < (mem_sizes/2); mem_cnt = mem_cnt + 1)
begin
Bank0[(mem_cnt*2)+1] = Bank0_32bit[mem_cnt][15:0];
Bank0[(mem_cnt*2)] = Bank0_32bit[mem_cnt][31:16];
end
`endif
end
 
// System clock generator
always begin
@ (posedge Clk) begin
1069,4 → 1125,36
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
 
task get_byte;
input [31:0] addr;
output [7:0] data;
reg [1:0] bank;
reg [15:0] short;
begin
bank = addr[24:23];
case(bank)
2'b00:
short = Bank0[addr[22:1]];
2'b01:
short = Bank1[addr[22:1]];
2'b10:
short = Bank2[addr[22:1]];
2'b11:
short = Bank3[addr[22:1]];
endcase // case (bank)
 
// Get the byte from the short
if (!addr[0])
data = short[15:8];
else
data = short[7:0];
 
//$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data);
end
endtask // get_byte
endmodule
/or1200_monitor.v
39,7 → 39,7
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP orpsoc_testbench.dut.or1200_top
`define OR1200_TOP orpsoc_testbench.dut.or1200_top0
 
//
// Define to enable lookup file generation
439,7 → 439,7
 
 
`ifdef VERSATILE_SDRAM
`define SDRAM_TOP design_testbench.sdram0
`define SDRAM_TOP orpsoc_testbench.sdram0
// Bit selects to define the bank
// 32 MB part with 4 banks
`define SDRAM_BANK_SEL_BITS 24:23
465,7 → 465,7
`endif // `ifdef VERSATILE_SDRAM
 
`ifdef XILINX_DDR2
`define DDR2_TOP design_testbench.gen_cs[0]
`define DDR2_TOP orpsoc_testbench.gen_cs[0]
// Gets instruction word from correct bank
task get_insn_from_xilinx_ddr2;
input [31:0] addr;

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