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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/orpsocv2/bench/verilog
    from Rev 49 to Rev 51
    Reverse comparison

Rev 49 → Rev 51

/smii_phy.v
147,10 → 147,10
 
// Allow us to check if RX DV has been low for a while
reg [3:0] rx_dv_long_low_sr;
wire dv_long_low;
wire rx_dv_long_low;
always @(posedge ethphy_mii_rx_clk)
rx_dv_long_low_sr[3:0] <= {rx_dv_long_low_sr[2:0], ethphy_mii_rx_dv};
assign rx_dv_long_low = ~(|rx_dv_long_low_sr);
assign rx_dv_long_low = ~(|rx_dv_long_low_sr[3:0]);
reg rx_dv;
wire [8:0] rx_fifo_out;
wire rx_fifo_empty,rx_fifo_almost_empty;

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