URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/bench/verilog
- from Rev 55 to Rev 57
- ↔ Reverse comparison
Rev 55 → Rev 57
/or1200_monitor.v
231,6 → 231,38
end |
endtask // display_arch_state |
|
// |
// Write state of the OR1200 registers into a file; version for exception |
// |
task display_arch_state_except; |
reg [5:0] i; |
reg [31:0] r; |
integer j; |
begin |
`ifdef OR1200_DISPLAY_ARCH_STATE |
ref = ref + 1; |
$fdisplay(flookup, "Instruction %d: %t", insns, $time); |
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn); |
for(i = 0; i < 32; i = i + 1) begin |
if (i % 4 == 0) |
$fdisplay(fexe); |
get_gpr(i, r); |
$fwrite(fexe, "GPR%d: %h ", i, r); |
end |
$fdisplay(fexe); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr; |
$fwrite(fexe, "SR : %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr; |
$fwrite(fexe, "EPCR0: %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear; |
$fwrite(fexe, "EEAR0: %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr; |
$fdisplay(fexe, "ESR0 : %h", r); |
insns = insns + 1; |
`endif |
end |
endtask // display_arch_state_except |
|
/* Keep a trace buffer of the last lot of instructions and addresses |
* "executed",as read from the writeback stage, and cause a $finish if we hit |
* an instruction that is invalid, such as all zeros. |
275,40 → 307,7
|
end |
endtask // monitor_for_crash |
|
|
// |
// Write state of the OR1200 registers into a file; version for exception |
// |
task display_arch_state_except; |
reg [5:0] i; |
reg [31:0] r; |
integer j; |
begin |
`ifdef OR1200_DISPLAY_ARCH_STATE |
ref = ref + 1; |
$fdisplay(flookup, "Instruction %d: %t", insns, $time); |
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn); |
for(i = 0; i < 32; i = i + 1) begin |
if (i % 4 == 0) |
$fdisplay(fexe); |
get_gpr(i, r); |
$fwrite(fexe, "GPR%d: %h ", i, r); |
end |
$fdisplay(fexe); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr; |
$fwrite(fexe, "SR : %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr; |
$fwrite(fexe, "EPCR0: %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear; |
$fwrite(fexe, "EEAR0: %h ", r); |
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr; |
$fdisplay(fexe, "ESR0 : %h", r); |
insns = insns + 1; |
`endif |
end |
endtask |
|
integer iwb_progress; |
reg [31:0] iwb_progress_addr; |
// |