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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/bench
    from Rev 353 to Rev 354
    ↔ Reverse comparison
  •

Rev 353 → Rev 354

/sysc/include/OrpsocMain.h
53,7 → 53,7
#define BENCH_RESET_TIME 10
 
//! CPU clock Half period in timescale units
#define BENCH_CLK_HALFPERIOD 20
#define BENCH_CLK_HALFPERIOD 10
 
//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
//! Currently is 32MB (8M words)
72,7 → 72,7
#define FLASH_END 0xf01fffff
 
//! Default port for RSP to listen on
#define DEFAULT_RSP_PORT 51000
#define DEFAULT_RSP_PORT 50003
 
//! FIFO size for talking to the RSP connection
#define RSP_FIFO_SIZE 8
/sysc/src/OrpsocMain.cpp
349,7 → 349,7
//printf("* Beginning test\n");
 
// Init the UART function
uart->initUart(25000000, 115200);
uart->initUart(50000000, 115200);
 
if (do_program_file_load) // Did the user specify a file to load?
{
/sysc/src/Or1200MonitorSC.cpp
188,6 → 188,7
}
}
}
/*
else if ((strcmp(argv[i], "-u")==0) ||
(strcmp(argv[i], "--bus-log")==0))
{
213,6 → 214,7
bus_trans_log_start_delay = log_start_time;
}
}
*/
}
}
 
375,7 → 377,9
printf(" -q, --quiet\t\tDisable the performance summary at end of simulation\n");
printf(" -m, --memdump <file> <0xstartaddr> <0xendaddr>\n\t\t\tDump data between <0xstartaddr> and <0xendaddr> from\n\t\t\tthe system's RAM to <file> in binary format on exit\n");
printf(" -c, --crash-monitor\tDetect when the processor has crashed and exit\n");
/*
printf(" -u, --bus-log <file> <val>\n\t\t\tLog the wishbone bus transactions to <file>, opt. start\n\t\t\tafter <val> ns\n\n");
*/
 
}
 
/verilog/uart_decoder.v
39,34 → 39,16
//// ////
//////////////////////////////////////////////////////////////////////
 
// Decodes UART signals sent over the line defined by UART_TX_LINE
 
// `include this file in the testbench and define UART_TX_LINE
// Uses define CLOCK_RATE as the frequency of the clock in Hz
 
// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
`timescale 1ns/1ns
module uart_decoder(clk, uart_tx);
 
// Requires definition of:
// CLK_RATE - frequency of system clock in Hz
// CLK_PERIOD - period of clock frequency in ns
// UART_BAUDRATE - otherwise defaults to 115200
// UART_TX_LINE - name of the UART output signal (normally a wire)
input clk;
input uart_tx;
 
// if it's not already defined, uses UART_BAUDRATE as baud to receive
// bytes at
`ifndef UART_BAUDRATE
`define UART_BAUDRATE 115200
`endif
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
 
`ifndef CLOCK_RATE
initial
begin
$display("* WARNING: uart_decoder included but CLOCK_RATE not defined.");
end
`else
`ifdef UART_TX_LINE
parameter UART_TX_WAIT = (`CLOCK_RATE / `UART_BAUDRATE) * `CLOCK_PERIOD;
// Something to trigger the task
always @(posedge clk)
uart_decoder;
74,50 → 56,38
task uart_decoder;
reg [7:0] tx_byte;
begin
while (`UART_TX_LINE !== 1'b1)
@(`UART_TX_LINE);
while (uart_tx !== 1'b1)
@(uart_tx);
// Wait for start bit
//while (`UART_TX_LINE == 1'b1)
while (`UART_TX_LINE !== 1'b0)
@(`UART_TX_LINE);
#(UART_TX_WAIT+(UART_TX_WAIT/2));
tx_byte[0] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[1] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[2] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[3] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[4] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[5] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[6] = `UART_TX_LINE;
#UART_TX_WAIT;
tx_byte[7] = `UART_TX_LINE;
#UART_TX_WAIT;
while (uart_tx !== 1'b0)
@(uart_tx);
#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
tx_byte[0] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[1] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[2] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[3] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[4] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[5] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[6] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[7] = uart_tx;
#uart_baudrate_period_ns;
//Check for stop bit
//if (`UART_TX_LINE == 1'b0)
if (`UART_TX_LINE !== 1'b1)
if (uart_tx !== 1'b1)
begin
//$display("* WARNING: user stop bit not received when expected at time %d__", $time);
// Wait for return to idle
//while (`UART_TX_LINE == 1'b0)
while (`UART_TX_LINE !== 1'b1)
@(`UART_TX_LINE);
//$display("* USER UART returned to idle at time %d",$time);
while (uart_tx !== 1'b1)
@(uart_tx);
end
// display the char
$write("%c", tx_byte);
end
endtask // user_uart_read_byte
`else // !`ifdef UART_TX_LINE
// If this file was included but not setup properly
initial
begin
$display("* WARNING: uart_decoder included but UART_TX_LINE not defined.");
end
`endif // !`ifdef UART_TX_LINE
`endif // !`ifndef CLOCK_RATE
 
endmodule // uart_decoder
/verilog/orpsoc_testbench_defines.v
39,15 → 39,12
//// ////
//////////////////////////////////////////////////////////////////////
 
// 25Mhz clock = 40ns period
`define CLOCK_PERIOD 40
`define CLOCK_RATE 25000000
// 50Mhz clock = 20ns period
`define CLOCK_PERIOD 20
 
// Period for 125MHz clock is 8ns
`define ETH_CLK_PERIOD 8
 
 
// The ORPSoC tests makefile should generate the test_define.v file in
// the sim/run directory.
`ifdef TEST_DEFINE_FILE
/verilog/orpsoc_testbench.v
329,10 → 329,15
// If we're using UART for printf output, include the
// UART decoder
`ifdef UART_PRINTF
// Define the UART's txt line for it to listen to
`define UART_TX_LINE uart0_stx_o
`define UART_BAUDRATE 115200
`include "uart_decoder.v"
uart_decoder
#(
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
)
uart0_decoder
(
.clk(clk),
.uart_tx(uart0_stx_o)
);
`endif
endmodule // orpsoc_testbench

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