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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/orpsocv2/bench
    from Rev 67 to Rev 69
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Rev 67 → Rev 69

/verilog/eth_phy_defines.v
49,7 → 49,7
//
 
// Address of PHY device (LXT971A)
`define ETH_PHY_ADDR 5'h00 //Changed to 0 -jb
`define ETH_PHY_ADDR 5'h07
 
// LED/Configuration pins on PHY device - see the specification, page 26, table 8
// Initial set of bits 13, 12 and 8 of Control Register

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