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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend
    from Rev 449 to Rev 542
    ↔ Reverse comparison
  •

Rev 449 → Rev 542

/par/bin/Makefile
19,34 → 19,19
# Name of the directory we're currently in
CUR_DIR=$(shell pwd)
 
VENDOR=actel
# The root path of the whole project
BOARD_ROOT ?=$(CUR_DIR)/../../..
include $(BOARD_ROOT)/Makefile.inc
 
VENDOR_TCL_SHELL=acttclsh
 
PROJECT_NAME=orpsoc
PROJECT_TOP_NAME=$(PROJECT_NAME)_top
PROJ_ADB_FILE_NAME=$(PROJECT_NAME).adb
DESIGN_TOP_NAME=$(DESIGN_NAME)_top
PROJ_ADB_FILE_NAME=$(DESIGN_NAME).adb
PROJ_ADB_FILE=$(PROJ_ADB_FILE_NAME)
 
# The root path of the whole project
BOARD_DIR ?=$(CUR_DIR)/../../..
PROJECT_ROOT=$(BOARD_DIR)/../../..
 
BOARD_RTL_PATH=$(BOARD_DIR)/rtl
BOARD_RTL_VERILOG_PATH=$(BOARD_RTL_PATH)/verilog
BOARD_RTL_VERILOG_INCLUDES=$(BOARD_RTL_VERILOG_PATH)/include
PROJECT_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDES)/$(PROJECT_NAME)-defines.v
 
SYN_PATH=$(BOARD_DIR)/syn/synplify
 
SW_PATH=$(PROJECT_ROOT)/sw
 
PAR_PATH=$(BOARD_DIR)/backend/par
PAR_RUN_PATH=$(PAR_PATH)/run
PAR_OUT_PATH=$(PAR_PATH)/out
 
# Required EDIF file names
EDIF_NAME=$(PROJECT_TOP_NAME).edn
PROJ_EDF_FILE=$(SYN_PATH)/out/$(EDIF_NAME)
EDIF_NAME=$(DESIGN_TOP_NAME).edn
PROJ_EDF_FILE=$(BOARD_SYN_DIR)/out/$(EDIF_NAME)
 
# TCL script names
TCL_SCRIPT_START=start.tcl
80,17 → 65,17
ROUTE_INCREMENTAL ?= off
PLACER_HIGH_EFFORT ?= off
 
PDC_FILE ?=$(PROJECT_NAME).pdc
SDC_FILE ?=$(PROJECT_NAME).sdc
PDC_FILE ?=$(DESIGN_NAME).pdc
SDC_FILE ?=$(DESIGN_NAME).sdc
 
 
DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(PROJECT_VERILOG_DEFINES) | cut -d ':' -f 1)
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
#DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(PROJECT_VERILOG_DEFINES) | cut -d ':' -f 1)
#DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
# Rule to look at what defines are being extracted from main file
print-defines:
@echo; echo "\t### Design defines ###"; echo
@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
@echo $(DESIGN_DEFINES)
#print-defines:
# @echo; echo "\t### Design defines ###"; echo
# @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
# @echo $(DESIGN_DEFINES)
 
# Rule to print out current config of current session
print-config:
109,15 → 94,6
@echo "\tBackend pinout script:"
@echo "\tBOARD_CONFIG="$(BOARD_CONFIG)
 
 
# Set V=1 when calling make to enable verbose output
# mainly for debugging purposes.
ifeq ($(V), 1)
Q=
else
Q ?=@
endif
 
TIME_CMD=time -p
 
# Rule for everything from, potentially, synthesis up to PAR
150,7 → 126,7
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_START)
 
$(PROJ_EDF_FILE):
$(MAKE) -C $(SYN_PATH)/run all
$(MAKE) -C $(BOARD_SYN_DIR)/run all
 
create-compile: create compile
 
158,11 → 134,11
rm -rf *.rpt *.log *~ *.tcl *.lok *.tmp *.dtf $(SDC_FILE) $(PDC_FILE) *.adb
 
clean-syn:
$(MAKE) -C $(SYN_PATH)/run distclean
$(MAKE) -C $(BOARD_SYN_DIR)/run distclean
 
clean-sw:
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
$(MAKE) -C $(SW_PATH)/lib distclean
$(MAKE) -C $(COMMON_SW_DIR)/lib distclean
 
 
distclean: clean-sw clean-syn clean
245,8 → 221,8
$(Q)rm -f $(TCL_FILE);
$(Q)echo; echo "\tGenerating "$(TCL_FILE); echo
$(Q)echo "set compile_directory "$(COMP_DIR) >> $(TCL_FILE)
$(Q)echo "set proj_name "$(PROJECT_NAME) >> $(TCL_FILE)
$(Q)echo "set top_name "$(PROJECT_TOP_NAME) >> $(TCL_FILE)
$(Q)echo "set proj_name "$(DESIGN_NAME) >> $(TCL_FILE)
$(Q)echo "set top_name "$(DESIGN_TOP_NAME) >> $(TCL_FILE)
$(Q)echo "set family "$(FPGA_FAMILY) >> $(TCL_FILE)
$(Q)echo "set part "$(FPGA_PART) >> $(TCL_FILE)
$(Q)echo "set package "$(FPGA_PACKAGE) >> $(TCL_FILE)
341,7 → 317,7
$(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE)
$(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE)
$(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE)
$(Q)echo " "$(PROJECT_NAME)"-timing.rpt " >> $(TCL_FILE)
$(Q)echo " "$(DESIGN_NAME)"-timing.rpt " >> $(TCL_FILE)
$(Q)echo " report " \\ >> $(TCL_FILE)
$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
$(Q)echo " -analysis max " \\ >> $(TCL_FILE)
349,7 → 325,7
$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
$(Q)echo " "$(PROJECT_NAME)"-timviol.rpt " >> $(TCL_FILE)
$(Q)echo " "$(DESIGN_NAME)"-timviol.rpt " >> $(TCL_FILE)
$(Q)echo " report " \\ >> $(TCL_FILE)
$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
$(Q)echo " -analysis min " \\ >> $(TCL_FILE)
357,7 → 333,7
$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
$(Q)echo " "$(PROJECT_NAME)"-timmindly.rpt " >> $(TCL_FILE)
$(Q)echo " "$(DESIGN_NAME)"-timmindly.rpt " >> $(TCL_FILE)
 
 
 

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