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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench
- from Rev 408 to Rev 409
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Rev 408 → Rev 409
/verilog/include/eth_stim.v
47,7 → 47,7
// Is straight forward when using RTL design, but if using netlist then paths to |
// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to |
// work with design put through Synplify, with hierarchy maintained. |
`define ETH_TOP dut.eth0 |
`define ETH_TOP dut.ethmac0 |
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram |
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0 |
|