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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include
- from Rev 542 to Rev 544
- ↔ Reverse comparison
Rev 542 → Rev 544
/orpsoc-defines.v
189,6 → 189,7
//`define GPIO0 |
`define ETH0 |
`define SMII0 |
`define SDC_CONTROLLER |
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`endif // `ifdef CUSTOM_MODULES_CONFIG |
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/orpsoc-params.v
129,6 → 129,12
parameter wbm_eth0_data_width = 32; |
parameter wbm_eth0_addr_width = 32; |
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// SDC controller defines |
parameter sdc_wb_adr = 8'h9e; |
parameter wbs_d_sdc_data_width = 32; |
parameter wbm_sdc_data_width = 32; |
parameter wbm_sdc_addr_width = 32; |
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// Memory sizing for wb_ram (simulation only) |
parameter internal_sram_mem_span = 32'h0080_0000; // 8MB |
parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024) |
165,10 → 171,11
/////////////////////////// |
// Has auto foward to last slave when no address hits |
parameter dbus_arb_wb_addr_match_width = 8; |
parameter dbus_arb_wb_num_slaves = 5; |
parameter dbus_arb_wb_num_slaves = 4; |
// Slave addresses |
parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM) |
parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0 |
parameter dbus_arb_slave2_adr = sdc_wb_adr; |
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/////////////////////////////// |
// // |
/sd_defines.v
0,0 → 1,89
//Read the documentation before changing values |
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`define BIG_ENDIAN |
//`define LITLE_ENDIAN |
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//`define SIM |
`define SYN |
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`define SDC_IRQ_ENABLE |
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`define ACTEL |
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//`define CUSTOM |
//`define ALTERA |
//`define XLINX |
//`define SIMULATOR |
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`define RESEND_MAX_CNT 3 |
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//MAX 255 BD |
//BD size/4 |
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`ifdef ACTEL |
`define BD_WIDTH 5 |
`define BD_SIZE 32 |
`define RAM_MEM_WIDTH_16 |
`define RAM_MEM_WIDTH 16 |
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`endif |
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//`ifdef CUSTOM |
// `define NR_O_BD_4 |
// `define BD_WIDTH 5 |
// `define BD_SIZE 32 |
// `define RAM_MEM_WIDTH_32 |
// `define RAM_MEM_WIDTH 32 |
//`endif |
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`ifdef SYN |
`define RESET_CLK_DIV 0 |
`define MEM_OFFSET 4 |
`endif |
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`ifdef SIM |
`define RESET_CLK_DIV 0 |
`define MEM_OFFSET 4 |
`endif |
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//SD-Clock Defines --------- |
//Use bus clock or a seperate clock |
`define SDC_CLK_BUS_CLK |
//`define SDC_CLK_SEP |
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// Use of internal clock divider |
//`define SDC_CLK_STATIC |
`define SDC_CLK_DYNAMIC |
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//SD DATA-transfer defines--- |
`define BLOCK_SIZE 512 |
`define SD_BUS_WIDTH_4 |
`define SD_BUS_W 4 |
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//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. |
//Add 18 for crc, endbit and z. |
`define BIT_BLOCK 1044 |
`define CRC_OFF 19 |
`define BIT_BLOCK_REC 1024 |
`define BIT_CRC_CYCLE 16 |
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//FIFO defines--------------- |
`define FIFO_RX_MEM_DEPTH 8 |
`define FIFO_RX_MEM_ADR_SIZE 4 |
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`define FIFO_TX_MEM_DEPTH 8 |
`define FIFO_TX_MEM_ADR_SIZE 4 |
//--------------------------- |
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