URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top
- from Rev 409 to Rev 439
- ↔ Reverse comparison
Rev 409 → Rev 439
/orpsoc_top.v
109,7 → 109,7
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rst_n_pad_i |
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) /* synthesis syn_global_buffers = 8; syn_hier = "flatten" */; |
)/* synthesis syn_global_buffers = 8; */; |
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`include "orpsoc-params.v" |
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1351,8 → 1351,8
.wbm0_stb_i (wbs_i_mc0_stb_i), |
.wbm0_dat_o (wbs_i_mc0_dat_o), |
.wbm0_ack_o (wbs_i_mc0_ack_o), |
.wbm0_err_o (), |
.wbm0_rty_o (), |
.wbm0_err_o (wbs_i_mc0_err_o), |
.wbm0_rty_o (wbs_i_mc0_rty_o), |
// Wishbone slave interface 1 |
.wbm1_dat_i (wbs_d_mc0_dat_i), |
.wbm1_adr_i (wbs_d_mc0_adr_i), |
1364,22 → 1364,29
.wbm1_stb_i (wbs_d_mc0_stb_i), |
.wbm1_dat_o (wbs_d_mc0_dat_o), |
.wbm1_ack_o (wbs_d_mc0_ack_o), |
.wbm1_err_o (), |
.wbm1_rty_o (), |
.wbm1_err_o (wbs_d_mc0_err_o), |
.wbm1_rty_o (wbs_d_mc0_rty_o), |
// Wishbone slave interface 2 |
.wbm2_dat_i (wbm_eth0_dat_o), |
.wbm2_adr_i (wbm_eth0_adr_o), |
.wbm2_sel_i (wbm_eth0_sel_o), |
.wbm2_cti_i (wbm_eth0_cti_o), |
.wbm2_bte_i (wbm_eth0_bte_o), |
.wbm2_we_i (wbm_eth0_we_o ), |
.wbm2_cyc_i (wbm_eth0_cyc_o), |
.wbm2_stb_i (wbm_eth0_stb_o), |
.wbm2_dat_o (wbm_eth0_dat_i), |
.wbm2_ack_o (wbm_eth0_ack_i), |
.wbm2_err_o (wbm_eth0_err_i), |
.wbm2_rty_o (wbm_eth0_rty_i), |
// Clock, reset |
.wb_clk_i (wb_clk), |
.wb_rst_i (wb_rst)); |
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assign wbs_i_mc0_err_o = 0; |
assign wbs_i_mc0_rty_o = 0; |
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assign wbs_d_mc0_err_o = 0; |
assign wbs_d_mc0_rty_o = 0; |
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defparam ram_wb0.aw = wb_aw; |
defparam ram_wb0.dw = wb_dw; |
defparam ram_wb0.mem_span = internal_sram_mem_span; |
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span; |
defparam ram_wb0.mem_size_bytes = internal_sram_mem_span; |
defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span; |
//////////////////////////////////////////////////////////////////////// |
`endif // `ifdef RAM_WB |
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