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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog
    from Rev 435 to Rev 439
    ↔ Reverse comparison
  •

Rev 435 → Rev 439

/include/orpsoc-params.v
122,15 → 122,6
parameter wbs_i_mc0_data_width = 32;
parameter wbs_d_mc0_data_width = 32;
 
// Memory sizing for synthesis (small)
parameter sdram_ba_width = 2;
// For 8MB part, mt16lc4m16a2
parameter sdram_row_width = 12;
parameter sdram_col_width = 8;
// For 32MB part, mt16lc4m16a2
//parameter sdram_row_width = 13;
//parameter sdram_col_width = 9;
 
// ETH0 defines
parameter eth0_wb_adr = 8'h92;
parameter wbs_d_eth0_data_width = 32;
138,9 → 129,9
parameter wbm_eth0_data_width = 32;
parameter wbm_eth0_addr_width = 32;
 
// Memory sizing for synthesis (small)
parameter internal_sram_mem_span = 32'h0080_0000;
parameter internal_sram_adr_width_for_span = 23;
// Memory sizing for wb_ram (simulation only)
parameter internal_sram_mem_span = 32'h0080_0000; // 8MB
parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024)
 
//////////////////////////////////////////////////////
// //
/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 11
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
217,16 → 217,16
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 9
`define ETH_RX_FIFO_CNT_WIDTH 8
`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 16
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 1
 
`define ETH_RX_FIFO_DATA_WIDTH 32
 
/orpsoc_top/orpsoc_top.v
109,7 → 109,7
 
rst_n_pad_i
 
) /* synthesis syn_global_buffers = 8; syn_hier = "flatten" */;
)/* synthesis syn_global_buffers = 8; */;
 
`include "orpsoc-params.v"
 
1351,8 → 1351,8
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (),
.wbm0_rty_o (),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
1364,22 → 1364,29
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (),
.wbm1_rty_o (),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (wbm_eth0_dat_o),
.wbm2_adr_i (wbm_eth0_adr_o),
.wbm2_sel_i (wbm_eth0_sel_o),
.wbm2_cti_i (wbm_eth0_cti_o),
.wbm2_bte_i (wbm_eth0_bte_o),
.wbm2_we_i (wbm_eth0_we_o ),
.wbm2_cyc_i (wbm_eth0_cyc_o),
.wbm2_stb_i (wbm_eth0_stb_o),
.wbm2_dat_o (wbm_eth0_dat_i),
.wbm2_ack_o (wbm_eth0_ack_i),
.wbm2_err_o (wbm_eth0_err_i),
.wbm2_rty_o (wbm_eth0_rty_i),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
 
assign wbs_i_mc0_err_o = 0;
assign wbs_i_mc0_rty_o = 0;
 
assign wbs_d_mc0_err_o = 0;
assign wbs_d_mc0_rty_o = 0;
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_span = internal_sram_mem_span;
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span;
defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
 

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