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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/actel
    from Rev 415 to Rev 425
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  •

Rev 415 → Rev 425

/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile
1,3 → 1,5
# Makefile is stripped out only to build SDR_16 controller.
 
VERSATILE_FIFO_PROJECT_FILES =versatile_fifo_dual_port_ram.v
VERSATILE_FIFO_PROJECT_FILES +=versatile_fifo_async_cmp.v
VERSATILE_FIFO_PROJECT_FILES +=dff_sr.v
31,34 → 33,32
fifo_fill.v: fifo_fill.fzm
perl fizzim.pl -encoding onehot < fifo_fill.fzm > fifo_fill.v
 
ddr_16_generated.v: ddr_16.fzm ddr_16_defines.v
perl fizzim.pl -encoding onehot < ddr_16.fzm > $@
#ddr_16_generated.v: ddr_16.fzm ddr_16_defines.v
# perl fizzim.pl -encoding onehot < ddr_16.fzm > $@
 
ddr_16.v: ddr_16_generated.v
vppreproc --simple $^ > $@
#ddr_16.v: ddr_16_generated.v
# vppreproc --simple $^ > $@
 
#fifo_adr_counter.v:
# @echo;echo "\tThis file,"$@", doesn't exist, is it still needed?!. \n\tMake will now stop";echo
# ls notexisting
 
VERSATILE_MEM_CTRL_IP_FILES=versatile_fifo_async_cmp.v async_fifo_mq.v versatile_fifo_dual_port_ram_dc_dw.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v ref_delay_counter.v pre_delay_counter.v burst_length_counter.v ddr_16.v fsm_wb.v delay.v ddr_ff.v dcm_pll.v dff_sr.v versatile_mem_ctrl_ddr.v ddr_16_defines.v sdr_16_defines.v codec.v gray_counter.v egress_fifo.v versatile_fifo_dual_port_ram_dc_sw.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v
 
versatile_mem_ctrl_ip.v: $(VERSATILE_MEM_CTRL_IP_FILES)
cat $^ | cat copyright.v - > $@
 
# SDRAM 16-bit wide databus dependency files - force a recompile
SDR_16_FILES=sdr_16_defines.v fsm_wb.v versatile_fifo_async_cmp.v async_fifo_mq.v delay.v codec.v gray_counter.v egress_fifo.v versatile_fifo_dual_port_ram_dc_sw.v dff_sr.v ref_counter.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v
sdr_16.v: $(SDR_16_FILES)
vppreproc +define+SDR_16 +incdir+. $^ > $@
 
 
# the single all rule
all: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v counter_csvs fifo_fill.v sdr_16.v ddr_16.v versatile_mem_ctrl_ip.v
#all: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v counter_csvs fifo_fill.v sdr_16.v ddr_16.v versatile_mem_ctrl_ip.v
all: sdr_16.v
 
 
 
clean:
rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
rm -rf fifo_fill.v sdr_16.v ddr_16.v
rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
# rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
rm -rf *_counter.v
rm -rf *.csv
rm -rf *~
/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
0,0 → 1,32
// true dual port RAM, sync
 
`ifdef ACTEL
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`endif
module vfifo_dual_port_ram_dc_sw
(
d_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
clk_b
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
/ordb1a3pe1500/sw/Makefile.inc
18,8 → 18,8
# This doesn't work! :-( Need to figure out way to set these and have them
# carry through to things like the liborpsoc driver modules etc.
#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
#export MARCH_FLAGS
MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
export MARCH_FLAGS
 
# Finally include the main software include file
 

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