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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/actel
    from Rev 435 to Rev 439
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  •

Rev 435 → Rev 439

/ordb1a3pe1500/bench/verilog/include/eth_stim.v
464,10 → 464,10
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM
// part
reg [21:0] buffer;
reg [7:0] sdram_byte;
reg [7:0] destram_byte;
reg [31:0] tx_len_bd;
integer i;
integer i,j;
integer failure;
begin
failure = 0;
496,20 → 496,46
// Variable we'll use for index in the PHY's TX buffer
buffer = 0; // Start of TX data
`ifdef VERSATILE_SDRAM
`ifdef RAM_WB
for (i=0;i<tx_len_bd;i=i+1)
begin
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
sdram0.get_byte(txpnt_sdram,sdram_byte);
destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
phy_byte = eth_phy0.tx_mem[buffer];
// Debugging output
//$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h,
//phy_byte = 0x%h", txpnt_sdram, destram_byte, buffer, phy_byte);
if (phy_byte !== destram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
failure = 1;
end
buffer = buffer + 1;
txpnt_sdram = txpnt_sdram+1;
end // for (i=0;i<tx_len_bd;i=i+1)
`else
`ifdef VERSATILE_SDRAM
for (i=0;i<tx_len_bd;i=i+1)
begin
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
sdram0.get_byte(txpnt_sdram,destram_byte);
 
phy_byte = eth_phy0.tx_mem[buffer];
// Debugging output
//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
if (phy_byte !== sdram_byte)
//$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, destram_byte, buffer, phy_byte);
if (phy_byte !== destram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
failure = 1;
end
519,12 → 545,15
end // for (i=0;i<tx_len_bd;i=i+1)
`else
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
`else // !`ifdef VERSATILE_SDRAM
 
$display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
tx_bd_addr, txpnt_wb);
$finish;
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef RAM_WB
if (failure)
begin
#100
963,8 → 992,7
reg [31:0] rxpnt_wb; // Pointer in array to where data should be
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
reg [15:0] sdram_short;
reg [7:0] sdram_byte;
//reg [7:0] phy_rx_mem [0:2000];
reg [7:0] destram_byte;
integer i;
integer failure;
1002,8 → 1030,31
rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
rxpnt_sdram = rx_bd_addr[24:0];
`ifdef VERSATILE_SDRAM
`ifdef RAM_WB
for (i=0;i<len;i=i+1)
begin
 
destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
 
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
 
if (phy_byte !== destram_byte)
begin
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, destram_byte);
failure = 1;
end
 
eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
eth_rx_sent_circbuf_size_mask;
 
rxpnt_sdram = rxpnt_sdram+1;
end
`else
`ifdef VERSATILE_SDRAM
// We'll look inside the SDRAM array
// Hard coded for the SDRAM buffer area to be from the halfway mark in
// memory (so starting in Bank2)
1016,15 → 1067,15
for (i=0;i<len;i=i+1)
begin
 
sdram0.get_byte(rxpnt_sdram,sdram_byte);
sdram0.get_byte(rxpnt_sdram,destram_byte);
 
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
 
if (phy_byte !== sdram_byte)
if (phy_byte !== destram_byte)
begin
// `TIME;
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
i, eth_rx_num_packets_checked, phy_byte, destram_byte);
failure = 1;
end
 
1034,15 → 1085,17
rxpnt_sdram = rxpnt_sdram+1;
end // for (i=0;i<len;i=i+2)
`else
`else
 
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
$display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
rx_bd_addr, rxpnt_wb);
$finish;
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef RAM_WB
 
if (failure)
begin
/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v
122,15 → 122,6
parameter wbs_i_mc0_data_width = 32;
parameter wbs_d_mc0_data_width = 32;
 
// Memory sizing for synthesis (small)
parameter sdram_ba_width = 2;
// For 8MB part, mt16lc4m16a2
parameter sdram_row_width = 12;
parameter sdram_col_width = 8;
// For 32MB part, mt16lc4m16a2
//parameter sdram_row_width = 13;
//parameter sdram_col_width = 9;
 
// ETH0 defines
parameter eth0_wb_adr = 8'h92;
parameter wbs_d_eth0_data_width = 32;
138,9 → 129,9
parameter wbm_eth0_data_width = 32;
parameter wbm_eth0_addr_width = 32;
 
// Memory sizing for synthesis (small)
parameter internal_sram_mem_span = 32'h0080_0000;
parameter internal_sram_adr_width_for_span = 23;
// Memory sizing for wb_ram (simulation only)
parameter internal_sram_mem_span = 32'h0080_0000; // 8MB
parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024)
 
//////////////////////////////////////////////////////
// //
/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 11
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
217,16 → 217,16
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 9
`define ETH_RX_FIFO_CNT_WIDTH 8
`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 16
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 1
 
`define ETH_RX_FIFO_DATA_WIDTH 32
 
/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
109,7 → 109,7
 
rst_n_pad_i
 
) /* synthesis syn_global_buffers = 8; syn_hier = "flatten" */;
)/* synthesis syn_global_buffers = 8; */;
 
`include "orpsoc-params.v"
 
1351,8 → 1351,8
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (),
.wbm0_rty_o (),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
1364,22 → 1364,29
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (),
.wbm1_rty_o (),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (wbm_eth0_dat_o),
.wbm2_adr_i (wbm_eth0_adr_o),
.wbm2_sel_i (wbm_eth0_sel_o),
.wbm2_cti_i (wbm_eth0_cti_o),
.wbm2_bte_i (wbm_eth0_bte_o),
.wbm2_we_i (wbm_eth0_we_o ),
.wbm2_cyc_i (wbm_eth0_cyc_o),
.wbm2_stb_i (wbm_eth0_stb_o),
.wbm2_dat_o (wbm_eth0_dat_i),
.wbm2_ack_o (wbm_eth0_ack_i),
.wbm2_err_o (wbm_eth0_err_i),
.wbm2_rty_o (wbm_eth0_rty_i),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
 
assign wbs_i_mc0_err_o = 0;
assign wbs_i_mc0_rty_o = 0;
 
assign wbs_d_mc0_err_o = 0;
assign wbs_d_mc0_rty_o = 0;
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_span = internal_sram_mem_span;
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span;
defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
 
/ordb1a3pe1500/backend/par/bin/Makefile
53,6 → 53,7
TCL_SCRIPT_COMPILE=compile.tcl
TCL_SCRIPT_PAR=par.tcl
TCL_SCRIPT_CREATE_COMPILE_PAR=create-compile-par.tcl
TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN=create-compile-par-bitgen.tcl
TCL_SCRIPT_REPORT=report.tcl
TCL_SCRIPT_BITGEN=bitgen.tcl
# Generate these every time
120,7 → 121,7
TIME_CMD=time -p
 
# Rule for everything from, potentially, synthesis up to PAR
all: print-config print-defines create-compile-par
all: print-config print-defines create-compile-par-bitgen
 
# Not possible to do programming file generation under Linux
# not with the free tools
131,6 → 132,9
create-compile-par: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
 
create-compile-par-bitgen: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
 
par: $(TCL_SCRIPT_PAR)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
 
223,6 → 227,17
$(Q)echo "\"">> $@
$(Q)echo >> $@
 
# Do project creation, compile and PAR in one single run of the tool
$(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN):
TCL_FILE=$@ $(MAKE) tcl-common
$(Q)echo "run_designer \"Create compile and PAR and generate programming file\" \" " >> $@
TCL_FILE=$@ $(MAKE) dump-actel-create-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-compile-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-par-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-bitgen-project-tcl
$(Q)echo "\"">> $@
$(Q)echo >> $@
 
# The different texts that we dump out for the different sets of command files
 
# This is the common header, setting variables in the TCL file
/ordb1a3pe1500/syn/synplify/bin/Makefile
112,7 → 112,7
SYN_LOG ?=syn.log
SYN_TOOL ?=synplify_pro # Name of the executable to call
# Options passed after the executable.
SYN_LICENSE_OPTS ?=-licensetype synplifypro_acteloem
SYN_LICENSE_OPTS ?=-licensetype synplifypro_actel
SYN_TOOL_OPTS ?=$(SYN_SCRIPT) $(SYN_LICENSE_OPTS) -batch -log $(SYN_LOG)
 
 

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