URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/actel
- from Rev 449 to Rev 468
- ↔ Reverse comparison
Rev 449 → Rev 468
/ordb1a3pe1500/sim/bin/Makefile
55,8 → 55,8
BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME) |
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# Export BOARD_PATH for the software makefiles |
BOARD_PATH=$(BOARD_DIR) |
export BOARD_PATH |
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME) |
export BOARD |
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# Paths to other important parts of this test suite |
COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl |
/ordb1a3pe1500/sw/bootrom/Makefile
14,10 → 14,10
bootrom.v: $(SW_ROOT)/bootrom/bootrom.v |
$(Q)cp -v $< . |
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export BOARD_PATH |
# Export BOARD so the Make script in the root software path knows we're to |
# use our board.h file, not theirs. |
export BOARD |
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# Pass BOARD_PATH so the Make script in the root software path knows we're to |
# use our board.h file, not theirs. |
$(SW_ROOT)/bootrom/bootrom.v: |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v |
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/ordb1a3pe1500/sw/Makefile.inc
9,10 → 9,10
SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw |
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# Set the BOARD_PATH to point to the root of this board build |
BOARD_PATH=$(shell pwd)/$(BOARD_SW_ROOT)/.. |
BOARD=actel/ordb1a3pe1500 |
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# Set RTL_VERILOG_INCLUDE_DIR so software |
RTL_VERILOG_INCLUDE_DIR=$(BOARD_PATH)/rtl/verilog/include |
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include |
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# Set the processor capability flags |
# This doesn't work! :-( Need to figure out way to set these and have them |
/ordb1a3pe1500/syn/synplify/bin/Makefile
16,9 → 16,9
BOARD_DIR ?=$(CUR_DIR)/../../.. |
PROJECT_ROOT=$(BOARD_DIR)/../../.. |
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# Export BOARD_PATH for the software makefiles |
BOARD_PATH=$(BOARD_DIR) |
export BOARD_PATH |
# Export BOARD for the software makefiles |
BOARD=actel/ordb1a3pe1500 |
export BOARD |
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DESIGN_NAME=orpsoc |
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