URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/actel
- from Rev 480 to Rev 485
- ↔ Reverse comparison
Rev 480 → Rev 485
/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
1001,7 → 1001,7
wire [10:0] or1200_dbg_wp_o; |
wire or1200_dbg_bp_o; |
wire or1200_dbg_rst; |
|
|
wire or1200_clk, or1200_rst; |
wire sig_tick; |
|
/ordb1a3pe1500/sw/Makefile.inc
8,7 → 8,8
# Figure out actual path the common software directory |
SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw |
|
# Set the BOARD_PATH to point to the root of this board build |
# Set the BOARD to be the path within the board/ path of the project that goes |
# to this project. |
BOARD=actel/ordb1a3pe1500 |
|
# Set RTL_VERILOG_INCLUDE_DIR so software |
/ordb1a3pe1500/sw/board/include/board.h
15,11 → 15,14
// Uncomment the appropriate bootloader define. This will effect the bootrom.S |
// file, which is compiled and converted into Verilog for inclusion at |
// synthesis time. See bootloader/bootloader.S for details on each option. |
|
#ifndef PRELOAD_RAM |
#define BOOTROM_SPI_FLASH |
//#define BOOTROM_GOTO_RESET |
//#define BOOTROM_LOOP_AT_ZERO |
//#define BOOTROM_LOOP_IN_ROM |
#else |
#define BOOTROM_GOTO_RESET |
#endif |
|
// |
// Defines for each core (memory map base, OR1200 interrupt line number, etc.) |
91,4 → 94,18
// |
#define TICKS_PER_SEC 100 |
|
// |
// UART driver initialisation |
// |
#define UART_NUM_CORES 3 |
|
#define UART_BASE_ADDRESSES_CSV \ |
UART0_BASE, UART2_BASE, UART2_BASE |
|
#define UART_BAUD_RATES_CSV \ |
UART0_BAUD_RATE, UART1_BAUD_RATE, UART1_BAUD_RATE |
|
|
|
|
#endif |