URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin
- from Rev 630 to Rev 638
- ↔ Reverse comparison
Rev 630 → Rev 638
/Makefile
81,65 → 81,54
|
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE) |
@echo; echo "\t#### Running NGDBuild ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \ |
$(NGC_FILE) $@ ) |
$(Q)ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) \ |
-uc $(UCF_FILE) $(NGC_FILE) $@ |
|
#This target uses Xilinx tools to perform Mapping |
$(MAPPED_NCD): $(NGD_FILE) |
@echo; echo "\t#### Mapping ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
map -p $(FPGA_PART) -detail -pr b \ |
-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)) |
$(Q)map -p $(FPGA_PART) -detail -pr b \ |
-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE) |
|
#This target uses Xilinx tools to Place & Route the design |
$(PARRED_NCD): $(MAPPED_NCD) |
@echo; echo "\t#### PAR'ing ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
par -w -ol high -xe n $(XILINX_FLAGS) $< $@ $(PCD_FILE) ) |
$(Q)par -w -ol high -xe n $(XILINX_FLAGS) $< $@ $(PCD_FILE) |
|
#This target uses Xilinx tools to generate a bitstream for download |
$(BIT_FILE): $(PARRED_NCD) |
@echo; echo "\t#### Generating .bit file ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ ) |
$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ |
|
$(BIT_FILE_FOR_SPI): $(PARRED_NCD) |
@echo; echo "\t#### Generating .bit file for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ ) |
$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ |
|
# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined. |
ifeq ($(BOOTLOADER_BIN),) |
$(MCS_FILE): $(BIT_FILE_FOR_SPI) |
@echo; echo "\t#### Generating .mcs file for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< ) |
$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< |
else |
$(MCS_FILE): $(BIT_FILE_FOR_SPI) |
@echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \ |
-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \ |
) |
$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \ |
-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) |
endif |
|
#this target downloads the bitstream to the target fpga |
download: $(BIT_FILE) $(BATCH_FILE) |
$(Q)( . ${XILINX_PATH}/settings32.sh && \ |
impact -batch $(BATCH_FILE) ) |
$(Q)impact -batch $(BATCH_FILE) |
|
#This target uses netgen to make a simulation netlist |
netlist: $(PARRED_NCD) |
@echo; echo "\t#### Generating netlist ####"; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \ |
netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<) |
$(Q)netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $< |
|
#This one uses TRCE to make a timing report |
timingreport: $(PARRED_NCD) |
@echo; echo "\t#### Generating timing report ####"; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \ |
trce $(TIMING_REPORT_OPTIONS) $< ) |
$(Q)trce $(TIMING_REPORT_OPTIONS) $< |
|
|
clean: |