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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/xilinx/atlys
    from Rev 633 to Rev 634
    ↔ Reverse comparison
  •

Rev 633 → Rev 634

/backend/bin/xilinx_ddr2_if_cache.ngc File deleted \ No newline at end of file
/syn/xst/coregen/xilinx_ddr2_if_cache.xco
0,0 → 1,93
##############################################################
#
# Xilinx Core Generator version 12.4
# Date: Sat Feb 5 19:21:34 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=8
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=xilinx_ddr2_if_cache
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=128
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=true
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=32
CSET write_width_b=128
# END Parameters
GENERATE
# CRC: 4eb8997c
/syn/xst/coregen/coregen.cgp
0,0 → 1,9
SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx45
SET package = csg324
SET speedgrade = -2
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
/syn/xst/bin/Makefile
84,6 → 84,9
NGC_FILE=$(DESIGN_NAME).ngc
NETLIST_FILE=$(DESIGN_NAME).v
 
COREGEN_DIR=$(BOARD_SYN_DIR)/coregen
COREGEN_CGP_FILE=$(COREGEN_DIR)/coregen.cgp
COREGEN_XCO_FILES=$(shell ls $(COREGEN_DIR)/*.xco)
 
XST_PRJ_FILE_SRC_DECLARE=verilog work
 
152,8 → 155,18
$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@
$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@
 
# Generate coregen cores
coregen:
$(Q)echo; echo "#### Running CORE Gen ####"; echo
$(Q)(. $(XILINX_SETTINGS_SCRIPT))
$(Q)$(shell cp $(COREGEN_XCO_FILES) .)
$(Q)$(shell cp $(COREGEN_CGP_FILE) .)
$(Q)for file in $(COREGEN_XCO_FILES); do \
coregen -b $(notdir $$file) -p $(notdir $(COREGEN_CGP_FILE)) $(XILINX_FLAGS); \
done
 
# XST command
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES) coregen
$(Q)echo; echo "\t#### Running XST ####"; echo;
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
$(Q)echo
168,7 → 181,7
 
 
clean:
$(Q)rm -rf *.* xst
$(Q)rm -rf *.* xst tmp _xmsgs xlnx_auto* *.lso
 
clean-sw:
$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean

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