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    /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
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Rev 69 → Rev 360

/WireDelay.v File deleted
/ml501_testbench_defines.v File deleted \ No newline at end of file
/ml501_testbench.v File deleted
/verilog/ddr2_model.v
0,0 → 1,2024
/****************************************************************************************
*
* File Name: ddr2.v
* Version: 5.80
* Model: BUS Functional
*
* Dependencies: ddr2_parameters.vh
*
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 1.00 JMK 07/29/03 Initial Release
* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH
* 2.20 JMK 08/07/03 General cleanup
* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
* Added AL_MIN and AL_MAX parameters.
* Removed support for OCD.
* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.
* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.
* 2.60 JMK 04/20/04 Fixed tWTR check.
* 2.70 JMK 04/30/04 Added tRFC maximum check.
* Combined Self Refresh and Power Down always blocks.
* Added Reset Function (CKE LOW Anytime).
* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active.
* Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
* tRFC maximum violation will only display one time.
* 2.90 JMK 11/05/04 Fixed DQS checking during write.
* Fixed false tRFC max assertion during power up and self ref.
* Added warning for 200us CKE low time during initialization.
* Added -3, -3E, and -37V speed grades to ddr2_parameters.v
* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.
* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
* Added ODT status messages.
* Updated the initialization sequence.
* Disable ODT and CLK pins during self refresh.
* Disable cmd and addr pins during power down and self refresh.
* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks.
* Changed tAXPD message from error to a warning.
* Added tDSS checking.
* Removed tDQSL checking during tWPRE and tWPST.
* Fixed a burst order error during writes.
* Renamed parameters file with .vh extension.
* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ.
* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge.
* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase.
* Clock jitter can be tolerated within specification range.
* Clock frequency is sampled from the CK pin.
* Scaleable up to 64 DQ and 16 DQS bits.
* Read data can be randomly skewed using RANDOM_OUT_DELAY.
* Parameterized read and write DQS, and read DQ.
* Initialization can be bypassed using initialize task.
* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined.
* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined.
* 4.30 JMK 02/15/06 Added dummy write to initialization sequence.
* Removed tWPST maximum checking.
* Rising dqs_n edge latches data when enabled in EMR.
* Fixed a sign error in the tJIT(cc) calculation.
* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined.
* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions.
* Fixed tRCD and tWTR checking.
* Errors entering Power Down or Self Refresh will cause reset.
* Ignore dqs_n when disabled in EMR.
* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh)
* Fixed tRFC max assertion during self refresh.
* Fixed tANPD checking during Power Down.
* Removed dummy write from initialization sequence.
* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
* Removed Auto Precharge error message during Power Down Enter.
* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n.
* RDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* tMOD changed from tCK units to ns units.
* Added 50 Ohm setting for Rtt in EMR.
* Improved checking of DQS during writes.
* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16.
* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble.
* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
* Added a register delay to ddr2_module.v when RDIMM is defined.
* Added multi-chip package model support in ddr2_mcp.v
* Added High Temp Self Refresh rate setting in EMRS2[7]
* 5.70 JMK 04/23/09 Updated tRPA definition
* Increased internal width to 72 bit DQ bus
* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open)
****************************************************************************************/
 
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
 
module ddr2_model (
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_rdqs,
ba,
addr,
dq,
dqs,
dqs_n,
rdqs_n,
odt
);
 
`include "ddr2_model_parameters.vh"
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 2*(AL_MAX + CL_MAX)
 
// Declare Ports
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_rdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] rdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
 
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
 
// Mode Registers
reg burst_order;
reg [BL_BITS:0] burst_length;
integer cas_latency;
integer additive_latency;
reg dll_reset;
reg dll_locked;
reg dll_en;
integer write_recovery;
reg low_power;
reg [1:0] odt_rtt;
reg odt_en;
reg [2:0] ocd;
reg dqs_n_en;
reg rdqs_en;
reg out_en;
integer read_latency;
integer write_latency;
 
// cmd encoding
parameter LOAD_MODE = 4'b0000;
parameter REFRESH = 4'b0001;
parameter PRECHARGE = 4'b0010;
parameter ACTIVATE = 4'b0011;
parameter WRITE = 4'b0100;
parameter READ = 4'b0101;
parameter NOP = 4'b0111;
parameter PWR_DOWN = 4'b1000;
parameter SELF_REF = 4'b100;
 
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
 
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_done;
integer init_step;
reg er_trfc_max;
reg odt_state;
reg prev_odt;
 
// cmd timers/counters
integer ref_cntr;
integer ck_cntr;
integer ck_load_mode;
integer ck_write;
integer ck_read;
integer ck_write_ap;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_cke;
integer ck_odt;
integer ck_dll_reset;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
time tm_refresh;
time tm_precharge;
time tm_precharge_all;
time tm_activate;
time tm_write_end;
time tm_self_refresh;
time tm_odt_en;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
 
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [35:0] check_write_postamble;
reg [35:0] check_write_preamble;
reg [35:0] check_write_dqs_high;
reg [35:0] check_write_dqs_low;
reg [17:0] check_dm_tdipw;
reg [71:0] check_dq_tdipw;
 
// data timers/counters
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [17:0];
time tm_dqs [17:0];
time tm_dqs_pos [35:0];
time tm_dqss_pos [35:0];
time tm_dqs_neg [35:0];
time tm_dq [71:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
 
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
 
// Memory Storage
`ifdef MAX_MEM
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used;
`endif
 
// receive
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [17:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [71:0] dq_in;
reg [35:0] dqs_in;
reg odt_in;
 
reg [17:0] dm_in_pos;
reg [17:0] dm_in_neg;
reg [71:0] dq_in_pos;
reg [71:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [35:0];
reg b2b_write;
reg [35:0] prev_dqs_in;
reg diff_ck;
 
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_rdqs) dm_in <= #BUS_DELAY dm_rdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
 
wire [17:0] dqs_even = dqs_in[17:0];
wire [17:0] dqs_odd = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
 
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
 
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
 
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
reset_task;
seed = RANDOM_SEED;
ck_cntr = 0;
end
 
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
 
`ifdef MAX_MEM
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
 
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
memory[addr] = data;
`else
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
 
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
data = memory[addr];
`else
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
 
// Before this task runs, the model must be in a valid state for precharge power down.
// After this task runs, NOP commands must be issued until tRFC has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, LOAD_MODE, 0, mode_reg0);
cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dqs_n_en = 0;
rdqs_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
odt_state = 0;
// reset bank state
active_bank = {`BANKS{1'b1}};
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
init_step = 0;
init_mode_reg = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
ocd = 0;
// exit power down and self refresh
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
// clear memory
`ifdef MAX_MEM
for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
memory[i] <= 'bx;
end
`else
memory_used <= 0; //erase memory
`endif
// clear maximum timing checks
tm_refresh <= 'bx;
for (i=0; i<`BANKS; i=i+1) begin
tm_bank_activate[i] <= 'bx;
end
end
endtask
 
task chk_err;
input samebank;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// all matching case expressions will be evaluated
casex ({samebank, fromcmd, cmd})
{1'b0, LOAD_MODE, 4'b0xxx } : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, LOAD_MODE, 4'b100x } : begin if (ck_cntr - ck_load_mode < TMRD) begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time); init_done = 0; end end
{1'b0, REFRESH , 4'b0xxx } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'b0, REFRESH , PWR_DOWN } : ; // 1 tCK
{1'b0, REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time); init_done = 0; end end
{1'b0, PRECHARGE, 4'b000x } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA)) $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
if (DEBUG && ($time - tm_bank_precharge[bank] < TRP)) $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank); end
{1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
{1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP)) begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time); init_done = 0; end end
{1'b0, ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task
{1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
{1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
|write_precharge_bank
|| (ck_cntr - ck_write_ap < 1)
|| (ck_cntr - ck_write < write_latency + burst_length/2 + 2)
|| ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end
{1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end
{1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end
endcase
end
endtask
 
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
begin
 
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, cmd);
chk_err(1'b1, bank, j, cmd);
end
chk_err(1'b0, bank, PWR_DOWN, cmd);
chk_err(1'b0, bank, SELF_REF, cmd);
end
 
case (cmd)
LOAD_MODE : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
case (bank)
0 : begin
// Burst Length
burst_length = 1<<addr[2:0];
if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = addr[6:4];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Test Mode
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
write_recovery = addr[11:9] + 1;
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if (!addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
end else if (addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
end
// ODT Rtt
odt_rtt = {addr[6], addr[2]};
if (odt_rtt == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if (odt_rtt == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b10) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
odt_en = 0;
end
// Additive Latency
additive_latency = addr[5:3];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end
// OCD Program
ocd = addr[9:7];
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
end else if (ocd == 3'b111) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
end
 
// DQS_N Enable
dqs_n_en = !addr[10];
if (!dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
end
// RDQS Enable
rdqs_en = addr[11];
if (!rdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (rdqs_en) begin
`ifdef x8
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
`else
$display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
rdqs_en = 0;
`endif
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
end
end
2 : begin
// High Temperature Self Refresh rate
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Disabled", $time, cmd_string[cmd], bank);
end else if (addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
end
if ((addr & ~(1<<7)) !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
if (addr !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
init_mode_reg[bank] = 1;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
end
end
PRECHARGE : begin
if (addr[AP]) begin
// tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
// the number of banks already open or closed.
for (i=0; i<`BANKS; i=i+1) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, i, j, cmd);
chk_err(1'b1, i, j, cmd);
end
chk_err(1'b0, i, PWR_DOWN, cmd);
chk_err(1'b0, i, SELF_REF, cmd);
end
if (|auto_precharge_bank) begin
$display ("%m: at time %t ERROR: %s All Failure. Auto Precharge is scheduled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
active_bank = 0;
tm_precharge_all <= $time;
end
end else begin
// A PRECHARGE command is allowed if there is no open row in that bank (idle state)
// or if the previously open row is already in the process of precharging.
// However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
active_bank[bank] = 1'b0;
tm_bank_precharge[bank] <= $time;
tm_precharge <= $time;
end
end
end
ACTIVATE : begin
if (`BANKS == 8) begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end
 
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_bank_activate[bank] <= $time;
tm_activate <= $time;
end
end
WRITE : begin
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
ck_bank_write[bank] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: %s prior to DLL locked. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
ck_bank_read[bank] <= ck_cntr;
ck_read <= ck_cntr;
end
end
NOP: begin
if (in_power_down) begin
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if (|active_bank & low_power) begin // slow exit active power down
ck_slow_exit_pd <= ck_cntr;
end
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time < 200000000)
$display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
// if (cmd_chk + 200000000 > $time)
// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && dll_reset) begin
active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges
ref_cntr = 0; // require refresh
init_step = init_step + 1;
end
end
3 : if (ref_cntr == 2) begin
init_step = init_step + 1;
end
4 : if (!dll_reset) init_step = init_step + 1;
5 : if (ocd == 3'b111) init_step = init_step + 1;
6 : begin
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, SELF_REF);
end
chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
chk_err(1'b0, bank, SELF_REF, SELF_REF);
if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (odt_en && odt_state) begin
$display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering slow_exit or precharge power down and tANPD has not been satisfied
if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, PWR_DOWN);
end
chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
 
if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
init_done = 0;
end
endcase
if (!init_done) begin
if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred. Device must be re-initialized.", $time);
reset_task;
end
end
prev_cke = cke;
end
endtask
 
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
 
if (diff_ck) begin
for (i=0; i<36; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<36; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
 
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
 
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
 
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
end
// write dqs
if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
 
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = burst_length;
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
end
// read dqs
if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
 
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = burst_length;
end
if (rdq_cntr > 0) begin // read data
dq_temp = memory_data>>(burst_position*DQ_BITS);
dq_out = dq_temp;
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
 
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
dqsck_max = dqsck[i] + TQHS + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
dqsck_min = dqsck[i] - TQHS - TDQSQ;
end
 
// DQSQ requirements
// 1.) less than tAC - DQSCK
// 2.) less than tDQSQ
// 3.) greater than -tAC
// 4.) greater than tQH from previous DQS edge
dqsq_min = -1*TAC;
if (dqsq_min < dqsck[i] - TQHS) begin
dqsq_min = dqsck[i] - TQHS;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TAC;
if (dqsq_max > TDQSQ + dqsck[i]) begin
dqsq_max = TDQSQ + dqsck[i];
end
 
dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if (dq_out_en) begin // tLZ2
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
end else begin // tHZ
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
end
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end else begin
out_delay = tck_avg/2.0;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
endtask
 
always @(diff_ck) begin : main
integer i;
 
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
 
// update current state
if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (write_recovery*tck_avg < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
dll_locked = 1;
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
 
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
ck_write_ap = ck_cntr;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus BL/2 cycles after Read command
// 3. tRTP after the last 4-bit prefetch
if (read_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
 
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
end
end
end
 
// respond to incoming command
if (cke_in ^ prev_cke) begin
ck_cke <= ck_cntr;
end
 
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
if (rd_pipeline[2*cas_latency - 1]) begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
end else begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
end
end
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_write_end <= $time;
end
end
 
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
 
if (dll_locked) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<50; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
endcase
end
 
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
$display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
$display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
 
// check tCL
if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
if (tcl_avg < TCL_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
end
 
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
 
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
 
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos <= $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked) begin
if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
if (tch_avg < TCH_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
end
 
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
 
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg <= $time;
end
 
// on die termination
if (odt_en) begin
// clk pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS) begin
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
end
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (odt_in && ($time - tm_odt_en < TMOD))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if ($time - tm_self_refresh < TXSNR)
$display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
 
// async ODT mode applies:
// 1.) during active power down with slow exit
// 2.) during precharge power down
// 3.) if tANPD has not been satisfied
// 4.) until tAXPD has been satisfied
if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
if (ck_cntr - ck_slow_exit_pd < TAXPD)
$display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
if (odt_in) begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
odt_state <= #(TAONPD) 1'b1;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
odt_state <= #(TAOFPD) 1'b0;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down with fast exit
end else begin
if (odt_in) begin
i = TAOND*2;
odt_pipeline[i] = 1'b1;
end else begin
i = TAOFD*2;
odt_pipeline[i] = 1'b1;
end
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
end
end
 
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
end
end
 
// receiver(s)
task dqs_even_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
 
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
always @(posedge dqs_even[16]) dqs_even_receiver(16);
always @(posedge dqs_even[17]) dqs_even_receiver(17);
 
task dqs_odd_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
 
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
// Processes to check hold and pulse width of control signals
always @(cke_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
tm_cke = $time;
end
always @(odt_in) begin
if (odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
end
tm_odt = $time;
end
 
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
 
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
 
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [4:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
 
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
always @(dm_in[16]) dm_timing_check(16);
always @(dm_in[17]) dm_timing_check(17);
 
task dq_timing_check;
input i;
reg [6:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
 
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
always @(dq_in[64]) dq_timing_check(64);
always @(dq_in[65]) dq_timing_check(65);
always @(dq_in[66]) dq_timing_check(66);
always @(dq_in[67]) dq_timing_check(67);
always @(dq_in[68]) dq_timing_check(68);
always @(dq_in[69]) dq_timing_check(69);
always @(dq_in[70]) dq_timing_check(70);
always @(dq_in[71]) dq_timing_check(71);
 
task dqs_pos_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
 
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
 
task dqs_neg_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_dqs_high[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
 
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
 
endmodule
/verilog/eth_stim.v
0,0 → 1,635
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench - Ethernet MAC Stimulus ////
//// ////
//// Description ////
//// Ethernet MAC stimulus tasks. Taken from the project ////
//// testbench in the ethmac core. ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// - Igor Mohor, igorM@opencores.org ////
//// - jb, jb@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
reg [15:0] rx_packet_length;
reg [7:0] st_data;
parameter Tp = 1;
initial
begin
 
repeat(170000) @(posedge eth_clk);
rx_packet_length = 16'd96; // Bytes
st_data = 8'h0F;
set_rx_packet(0, rx_packet_length, 1'b0, 48'h0012_3456_789a, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
append_rx_crc(0, rx_packet_length, 1'b0, 1'b0);
 
/*
// write to phy's control register for 10Mbps
#Tp eth_phy0.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
#Tp eth_phy0.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
*/
/*
// write to phy's control register for 100Mbps
#Tp eth_phy0.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
#Tp eth_phy0.control_bit8_0 = 9'h1_00; // bit 6 reset - (10/100), bit 8 set - FD
*/
 
//#Tp eth_phy0.carrier_sense_tx_fd_detect(1); // Full duplex CRS detect normally off
 
/*
from eth_phy.v:
task send_rx_packet;
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
input [31:0] start_addr; // start address
input [31:0] len; // length of frame in Bytes (without preamble and SFD)
input plus_drible_nibble; // if length is longer for one nibble
*/
// while (1)
// begin
#300000 eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, rx_packet_length, 1'b0);
//end
/* TODO: Some checking here that the packet's contents actually ended up in RAM correctly */
end
/*
TASKS for set and check RX packets:
-----------------------------------
set_rx_packet
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
check_rx_packet
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
*/
task set_rx_packet;
input [31:0] rxpnt; // pointer to place in in the phy rx buffer we'll start at
input [15:0] len;
input plus_dribble_nibble; // if length is longer for one nibble
input [47:0] eth_dest_addr;
input [47:0] eth_source_addr;
input [15:0] eth_type_len;
input [7:0] eth_start_data;
integer i, sd;
reg [47:0] dest_addr;
reg [47:0] source_addr;
reg [15:0] type_len;
reg [21:0] buffer;
reg delta_t;
begin
buffer = rxpnt[21:0];
dest_addr = eth_dest_addr;
source_addr = eth_source_addr;
type_len = eth_type_len;
sd = eth_start_data;
delta_t = 0;
for(i = 0; i < len; i = i + 1)
begin
if (i < 6)
begin
eth_phy0.rx_mem[buffer] = dest_addr[47:40];
dest_addr = dest_addr << 8;
end
else if (i < 12)
begin
eth_phy0.rx_mem[buffer] = source_addr[47:40];
source_addr = source_addr << 8;
end
else if (i < 14)
begin
eth_phy0.rx_mem[buffer] = type_len[15:8];
type_len = type_len << 8;
end
else
begin
eth_phy0.rx_mem[buffer] = sd[7:0];
sd = sd + 1;
end
buffer = buffer + 1;
end
delta_t = !delta_t;
if (plus_dribble_nibble)
eth_phy0.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
delta_t = !delta_t;
end
endtask // set_rx_packet
 
 
 
 
task set_rx_addr_type;
input [31:0] rxpnt;
input [47:0] eth_dest_addr;
input [47:0] eth_source_addr;
input [15:0] eth_type_len;
integer i;
reg [47:0] dest_addr;
reg [47:0] source_addr;
reg [15:0] type_len;
reg [21:0] buffer;
reg delta_t;
begin
buffer = rxpnt[21:0];
dest_addr = eth_dest_addr;
source_addr = eth_source_addr;
type_len = eth_type_len;
delta_t = 0;
for(i = 0; i < 14; i = i + 1)
begin
if (i < 6)
begin
eth_phy0.rx_mem[buffer] = dest_addr[47:40];
dest_addr = dest_addr << 8;
end
else if (i < 12)
begin
eth_phy0.rx_mem[buffer] = source_addr[47:40];
source_addr = source_addr << 8;
end
else // if (i < 14)
begin
eth_phy0.rx_mem[buffer] = type_len[15:8];
type_len = type_len << 8;
end
buffer = buffer + 1;
end
delta_t = !delta_t;
end
endtask // set_rx_addr_type
 
/*
task check_rx_packet;
input [31:0] rxpnt_phy; // source
input [31:0] rxpnt_wb; // destination
input [15:0] len;
input plus_dribble_nibble; // if length is longer for one nibble
input successful_dribble_nibble; // if additional nibble is stored into memory
output [31:0] failure;
integer i, data_wb, data_phy;
reg [31:0] addr_wb, addr_phy;
reg [31:0] failure;
reg [21:0] buffer;
reg delta_t;
begin
addr_phy = rxpnt_phy;
addr_wb = rxpnt_wb;
delta_t = 0;
failure = 0;
 
// First write might not be word allign.
if(addr_wb[1:0] == 1)
begin
wb_slave.rd_mem(addr_wb[21:0] - 1, data_wb, 4'h7);
data_phy[31:24] = 0;
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0]];
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0] + 1];
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0] + 2];
i = 3;
if (data_phy[23:0] !== data_wb[23:0])
begin
//`TIME;
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
//$display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
failure = 1;
end
end
else if (addr_wb[1:0] == 2)
begin
wb_slave.rd_mem(addr_wb[21:0] - 2, data_wb, 4'h3);
data_phy[31:16] = 0;
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0]];
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0] + 1];
i = 2;
if (data_phy[15:0] !== data_wb[15:0])
begin
//`TIME;
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
//$display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
failure = 1;
end
end
else if (addr_wb[1:0] == 3)
begin
wb_slave.rd_mem(addr_wb[21:0] - 3, data_wb, 4'h1);
data_phy[31: 8] = 0;
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0]];
i = 1;
if (data_phy[7:0] !== data_wb[7:0])
begin
//`TIME;
//$display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
//$display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
failure = 1;
end
end
else
i = 0;
delta_t = !delta_t;
 
for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
begin
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i];
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0] + i + 1];
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0] + i + 2];
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0] + i + 3];
if (data_phy[31:0] !== data_wb[31:0])
begin
//`TIME;
//if (i == 0)
// $display(" addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
//$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
failure = failure + 1;
end
end
delta_t = !delta_t;
 
// Last word
if((len - i) == 3)
begin
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i];
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0] + i + 1];
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0] + i + 2];
if (plus_dribble_nibble)
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0] + i + 3];
else
data_phy[ 7: 0] = 0;
if (data_phy[31:8] !== data_wb[31:8])
begin
//`TIME;
//$display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
failure = failure + 1;
end
if (plus_dribble_nibble && successful_dribble_nibble)
begin
if (data_phy[3:0] !== data_wb[3:0])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
else if (plus_dribble_nibble && !successful_dribble_nibble)
begin
if (data_phy[3:0] === data_wb[3:0])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
end
else if((len - i) == 2)
begin
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hE);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i];
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0] + i + 1];
if (plus_dribble_nibble)
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0] + i + 2];
else
data_phy[15: 8] = 0;
data_phy[ 7: 0] = 0;
if (data_phy[31:16] !== data_wb[31:16])
begin
//`TIME;
//$display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
failure = failure + 1;
end
if (plus_dribble_nibble && successful_dribble_nibble)
begin
if (data_phy[11:8] !== data_wb[11:8])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
else if (plus_dribble_nibble && !successful_dribble_nibble)
begin
if (data_phy[11:8] === data_wb[11:8])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
end
else if((len - i) == 1)
begin
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hC);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i];
if (plus_dribble_nibble)
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0] + i + 1];
else
data_phy[23:16] = 0;
data_phy[15: 8] = 0;
data_phy[ 7: 0] = 0;
if (data_phy[31:24] !== data_wb[31:24])
begin
//`TIME;
//$display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
failure = failure + 1;
end
if (plus_dribble_nibble && successful_dribble_nibble)
begin
if (data_phy[19:16] !== data_wb[19:16])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
else if (plus_dribble_nibble && !successful_dribble_nibble)
begin
if (data_phy[19:16] === data_wb[19:16])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
failure = failure + 1;
end
end
end
else if((len - i) == 4)
begin
wb_slave.rd_mem(addr_wb[21:0] + i, data_wb, 4'hF);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i];
data_phy[23:16] = eth_phy0.rx_mem[addr_phy[21:0] + i + 1];
data_phy[15: 8] = eth_phy0.rx_mem[addr_phy[21:0] + i + 2];
data_phy[ 7: 0] = eth_phy0.rx_mem[addr_phy[21:0] + i + 3];
if (data_phy[31:0] !== data_wb[31:0])
begin
//`TIME;
//$display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
failure = failure + 1;
end
if (plus_dribble_nibble)
begin
wb_slave.rd_mem(addr_wb[21:0] + i + 4, data_wb, 4'h8);
data_phy[31:24] = eth_phy0.rx_mem[addr_phy[21:0] + i + 4];
if (successful_dribble_nibble)
begin
if (data_phy[27:24] !== data_wb[27:24])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
failure = failure + 1;
end
end
else
begin
if (data_phy[27:24] === data_wb[27:24])
begin
//`TIME;
//$display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
failure = failure + 1;
end
end
end
end
else
$display("(%0t)(%m) ERROR", $time);
delta_t = !delta_t;
end
endtask // check_rx_packet
*/
//////////////////////////////////////////////////////////////
// Ethernet CRC Basic tasks
//////////////////////////////////////////////////////////////
 
task append_rx_crc;
input [31:0] rxpnt_phy; // source
input [15:0] len; // length in bytes without CRC
input plus_dribble_nibble; // if length is longer for one nibble
input negated_crc; // if appended CRC is correct or not
reg [31:0] crc;
reg [7:0] tmp;
reg [31:0] addr_phy;
reg delta_t;
begin
addr_phy = rxpnt_phy + len;
delta_t = 0;
// calculate CRC from prepared packet
paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
if (negated_crc)
crc = ~crc;
delta_t = !delta_t;
 
if (plus_dribble_nibble)
begin
tmp = eth_phy0.rx_mem[addr_phy];
eth_phy0.rx_mem[addr_phy] = {crc[27:24], tmp[3:0]};
eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
end
else
begin
eth_phy0.rx_mem[addr_phy] = crc[31:24];
eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
end
end
endtask // append_rx_crc
 
task append_rx_crc_delayed;
input [31:0] rxpnt_phy; // source
input [15:0] len; // length in bytes without CRC
input plus_dribble_nibble; // if length is longer for one nibble
input negated_crc; // if appended CRC is correct or not
reg [31:0] crc;
reg [7:0] tmp;
reg [31:0] addr_phy;
reg delta_t;
begin
addr_phy = rxpnt_phy + len;
delta_t = 0;
// calculate CRC from prepared packet
paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
if (negated_crc)
crc = ~crc;
delta_t = !delta_t;
 
if (plus_dribble_nibble)
begin
tmp = eth_phy0.rx_mem[addr_phy];
eth_phy0.rx_mem[addr_phy] = {crc[27:24], tmp[3:0]};
eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
end
else
begin
eth_phy0.rx_mem[addr_phy] = crc[31:24];
eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
end
end
endtask // append_rx_crc_delayed
 
 
// paralel CRC calculating for PHY RX
task paralel_crc_phy_rx;
input [31:0] start_addr; // start address
input [31:0] len; // length of frame in Bytes without CRC length
input plus_dribble_nibble; // if length is longer for one nibble
output [31:0] crc_out;
reg [21:0] addr_cnt; // only 22 address lines
integer word_cnt;
integer nibble_cnt;
reg [31:0] load_reg;
reg delta_t;
reg [31:0] crc_next;
reg [31:0] crc;
reg crc_error;
reg [3:0] data_in;
integer i;
begin
#1 addr_cnt = start_addr[21:0];
word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
crc = 32'hFFFF_FFFF; // INITIAL value
delta_t = 0;
// length must include 4 bytes of ZEROs, to generate CRC
// get number of nibbles from Byte length (2^1 = 2)
if (plus_dribble_nibble)
nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
else
nibble_cnt = ((len + 4) << 1);
// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
while (nibble_cnt > 0)
begin
// wait for delta time
delta_t = !delta_t;
// shift data in
 
if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
data_in[3:0] = 4'h0;
else
 
data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
crc_next[0] = (data_in[0] ^ crc[28]);
crc_next[1] = (data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29]);
crc_next[2] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[30]);
crc_next[3] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30] ^ crc[31]);
crc_next[4] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[0];
crc_next[5] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[1];
crc_next[6] = (data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30]) ^ crc[ 2];
crc_next[7] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[3];
crc_next[8] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[4];
crc_next[9] = (data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30]) ^ crc[5];
crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[6];
crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[7];
crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[30]) ^ crc[8];
crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30] ^ crc[31]) ^ crc[9];
crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30] ^ crc[31]) ^ crc[10];
crc_next[15] = (data_in[3] ^ crc[31]) ^ crc[11];
crc_next[16] = (data_in[0] ^ crc[28]) ^ crc[12];
crc_next[17] = (data_in[1] ^ crc[29]) ^ crc[13];
crc_next[18] = (data_in[2] ^ crc[30]) ^ crc[14];
crc_next[19] = (data_in[3] ^ crc[31]) ^ crc[15];
crc_next[20] = crc[16];
crc_next[21] = crc[17];
crc_next[22] = (data_in[0] ^ crc[28]) ^ crc[18];
crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29] ^ crc[28]) ^ crc[19];
crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30] ^ crc[29]) ^ crc[20];
crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31] ^ crc[30]) ^ crc[21];
crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31] ^ crc[28]) ^ crc[22];
crc_next[27] = (data_in[1] ^ crc[29]) ^ crc[23];
crc_next[28] = (data_in[2] ^ crc[30]) ^ crc[24];
crc_next[29] = (data_in[3] ^ crc[31]) ^ crc[25];
crc_next[30] = crc[26];
crc_next[31] = crc[27];
 
crc = crc_next;
crc_error = crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
case (nibble_cnt)
9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
!crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
!crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
!crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
default: crc_out = crc_out;
endcase
// wait for delta time
delta_t = !delta_t;
// increment address and load new data
if ((word_cnt+3) == 7)//4)
begin
// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
addr_cnt = addr_cnt + 1;
end
// set new load bit position
if((word_cnt+3) == 31)
word_cnt = 16;
else if ((word_cnt+3) == 23)
word_cnt = 8;
else if ((word_cnt+3) == 15)
word_cnt = 0;
else if ((word_cnt+3) == 7)
word_cnt = 24;
else
word_cnt = word_cnt + 4;// - 4;
// decrement nibble counter
nibble_cnt = nibble_cnt - 1;
// wait for delta time
delta_t = !delta_t;
end // while
#1;
end
endtask // paralel_crc_phy_rx
/verilog/eth_phy_defines.v
0,0 → 1,91
//////////////////////////////////////////////////////////////////////
//// ////
//// File name: eth_phy_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
//
//
 
// Address of PHY device (LXT971A)
`define ETH_PHY_ADDR 5'h07
 
// LED/Configuration pins on PHY device - see the specification, page 26, table 8
// Initial set of bits 13, 12 and 8 of Control Register
`define LED_CFG1 1'b0
`define LED_CFG2 1'b1
`define LED_CFG3 1'b1
 
 
// Supported speeds and physical ports - see the specification, page 67, table 41
// Set bits 15 to 9 of Status Register
`define SUPPORTED_SPEED_AND_PORT 7'h3F
 
// Extended status register (address 15)
// Set bit 8 of Status Register
`define EXTENDED_STATUS 1'b0
 
// Default status bits - see the specification, page 67, table 41
// Set bits 6 to 0 of Status Register
`define DEFAULT_STATUS 7'h09
 
// PHY ID 1 number - see the specification, page 68, table 42
// Set bits of Phy Id Register 1
`define PHY_ID1 16'h0013
 
// PHY ID 2 number - see the specification, page 68, table 43
// Set bits 15 to 10 of Phy Id Register 2
`define PHY_ID2 6'h1E
 
// Manufacturer MODEL number - see the specification, page 68, table 43
// Set bits 9 to 4 of Phy Id Register 2
`define MAN_MODEL_NUM 6'h0E
 
// Manufacturer REVISION number - see the specification, page 68, table 43
// Set bits 3 to 0 of Phy Id Register 2
`define MAN_REVISION_NUM 4'h2
 
 
 
 
/verilog/ml501_testbench.v
0,0 → 1,535
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC on ml501 testbench ////
//// ////
//// Description ////
//// ORPSoC Testbench file ////
//// ////
//// To Do: ////
//// Update ethernet and SPI models appropriately ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius.baxter@orsoc.se ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1ns/1ps
`include "glbl.v"
`include "ml501_defines.v"
`include "ml501_testbench_defines.v"
 
module ml501_testbench();
 
reg clk, clk_200;
reg rst_n;
wire clk_200_p, clk_200_n;
// Setup global clock. Period defined in orpsoc_testbench_defines.v
initial
begin
clk <= 0;
clk_200 <= 0;
rst_n <= 1;
end
 
always
#2500 clk_200 <= ~clk_200;
always
#((`CLOCK_PERIOD)/2) clk <= ~clk;
 
assign clk_200_p = clk_200;
assign clk_200_n = ~clk_200;
// Assert rst_n and then bring it low again
initial
begin
repeat (4) @(negedge clk);
rst_n <= 0;
repeat (16) @(negedge clk);
rst_n <= 1;
end
 
 
wire usr_rst_in, usr_rst_out;
assign usr_rst_in = usr_rst_out;
// Wires for the dut
wire spi_sd_sclk_o;
wire spi_sd_ss_o;
wire spi_sd_miso_i;
wire spi_sd_mosi_o;
 
`ifdef ML501_MEMORY_SSRAM
wire `tsramtrace sram_clk;
wire sram_clk_fb;
wire `tsramtrace sram_adv_ld_n;
wire [3:0] `tsramtrace sram_bw;
wire `tsramtrace sram_cen;
wire [21:1] `tsramtrace sram_flash_addr;
wire [31:0] `tsramtrace sram_flash_data;
wire `tsramtrace sram_flash_oe_n;
wire `tsramtrace sram_flash_we_n;
wire `tsramtrace sram_mode;
`endif // `ifdef ML501_MEMORY_SSRAM
 
 
`ifdef ML501_MEMORY_DDR2
 
`include "ml501_ddr2_params.vh"
localparam DEVICE_WIDTH = 16; // Memory device data width
localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
localparam real TCYC_200 = 5.0;
localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
 
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [CLK_WIDTH-1:0] ddr2_ck_sdram;
reg [CLK_WIDTH-1:0] ddr2_ck_n_sdram;
reg [ROW_WIDTH-1:0] ddr2_a_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
reg [CS_WIDTH-1:0] ddr2_cs_n_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram;
 
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [CLK_WIDTH-1:0] ddr2_ck_fpga;
wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_a_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CS_WIDTH-1:0] ddr2_cs_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
`endif
`ifdef USE_SPI_FLASH
wire spi_flash_sclk_o;
wire spi_flash_ss_o;
wire spi_flash_miso_i;
wire spi_flash_mosi_o;
wire spi_flash_w_n_o;
wire spi_flash_hold_n_o;
`endif
 
`ifdef USE_ETHERNET
wire phy_tx_clk;
wire [3:0] phy_tx_data;
wire phy_tx_en;
wire phy_tx_er;
wire phy_rx_clk;
wire [3:0] phy_rx_data;
wire phy_dv;
wire phy_rx_er;
wire phy_col;
wire phy_crs;
wire phy_smi_clk;
wire phy_smi_data;
wire phy_rst_n;
`endif
wire spi1_mosi_o;
wire spi1_miso_i;
wire spi1_ss_o;
wire spi1_sclk_o;
wire [25:0] gpio;
wire uart0_srx_i;
wire uart0_stx_o;
wire dbg_tdi_i;
wire dbg_tck_i;
wire dbg_tms_i;
wire dbg_tdo_o;
wire rst_i;
wire rst_o;
wire clk_i;
 
assign clk_i = clk;
assign rst_i = rst_n;
 
// Tie off some inputs
assign spi1_miso_i = 0;
assign uart0_srx_i = 1;
 
ml501 dut
(
.sys_rst_in (rst_i),
.sys_clk_in (clk_i),
.sys_clk_in_p (clk_200_p),
.sys_clk_in_n (clk_200_n),
.usr_rst_in (usr_rst_in),
.usr_rst_out (usr_rst_out),
 
// UART
.uart0_RX(uart0_srx_i),
.uart0_TX(uart0_stx_o),
// Duplicates of the UART signals, this time to the USB debug cable
.uart0_RX_expheader(uart0_srx_i),
.uart0_TX_expheader(uart0_stx_o),
// JTAG
.dbg_tdo_pad_o (dbg_tdo_o),
.dbg_tdi_pad_i (dbg_tdi_i),
.dbg_tck_pad_i (dbg_tck_i),
.dbg_tms_pad_i (dbg_tms_i),
 
`ifdef USE_ETHERNET
.phy_tx_clk(phy_tx_clk),
.phy_tx_data(phy_tx_data),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.phy_col(phy_col),
.phy_crs(phy_crs),
.phy_smi_clk(phy_smi_clk),
.phy_smi_data(phy_smi_data),
.phy_rst_n(phy_rst_n),
`endif
`ifdef ML501_MEMORY_SSRAM
// ZBT SSRAM
.sram_clk (sram_clk),
.sram_flash_addr (sram_flash_addr),
.sram_cen (sram_cen),
.sram_flash_oe_n (sram_flash_oe_n),
.sram_flash_we_n (sram_flash_we_n),
.sram_bw (sram_bw),
.sram_adv_ld_n (sram_adv_ld_n),
.sram_mode (sram_mode),
.sram_clk_fb (sram_clk_fb),
.sram_flash_data (sram_flash_data),
`endif // `ifdef ML501_MEMORY_SSRAM
 
`ifdef ML501_MEMORY_DDR2
.ddr2_a (ddr2_a_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_odt (ddr2_odt_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_ck (ddr2_ck_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs (ddr2_dqs_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
`endif // `ifdef ML501_MEMORY_DDR2
`ifdef USE_SPI_FLASH
.spi_flash_sclk_pad_o (spi_flash_sclk_o),
.spi_flash_ss_pad_o (spi_flash_ss_o),
.spi_flash_mosi_pad_o (spi_flash_mosi_o),
.spi_flash_w_n_pad_o (spi_flash_w_n_o),
.spi_flash_hold_n_pad_o (spi_flash_hold_n_o),
.spi_flash_miso_pad_i (spi_flash_miso_i),
`endif
// GPIO
.gpio (gpio)
);
`ifndef POST_SYNTHESIS_SIM
// Make the RF be quiet
defparam dut.i_or1k.i_or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.SIM_COLLISION_CHECK = "NONE";
defparam dut.i_or1k.i_or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.SIM_COLLISION_CHECK = "NONE";
`endif
`ifdef VPI_DEBUG_ENABLE
// Debugging interface
vpi_debug_module vpi_dbg(
.tms(dbg_tms_i),
.tck(dbg_tck_i),
.tdi(dbg_tdi_i),
.tdo(dbg_tdo_o));
`else
// If no VPI debugging, tie off JTAG inputs
assign dbg_tdi_i = 1;
assign dbg_tck_i = 0;
assign dbg_tms_i = 1;
`endif
 
`ifdef USE_ETHERNET
eth_phy eth_phy0
(
// Outputs
.mtx_clk_o (phy_tx_clk),
.mrx_clk_o (phy_rx_clk),
.mrxd_o (phy_rx_data),
.mrxdv_o (phy_dv),
.mrxerr_o (phy_rx_er),
.mcoll_o (phy_col),
.mcrs_o (phy_crs),
// Inouts
.md_io (phy_smi_data),
// Inputs
.m_rst_n_i (phy_rst_n),
.mtxd_i (phy_tx_data),
.mtxen_i (phy_tx_en),
.mtxerr_i (phy_tx_er),
.mdc_i (phy_smi_clk));
`endif
 
// External memories, if enabled
 
`ifdef ML501_MEMORY_SSRAM
wire [18:0] sram_a;
wire [3:0] dqp;
assign sram_a[18:0] = sram_flash_addr[19:1];
wire sram_ce1b, sram_ce2, sram_ce3b;
assign sram_ce1b = 1'b0;
assign sram_ce2 = 1'b1;
assign sram_ce3b = 1'b0;
assign sram_clk_fb = sram_clk;
 
cy7c1354 ssram0
(
// Inouts
// This model puts each parity bit after each byte, but the ML501's part
// doesn't, so we wire up the data bus like so.
.d ({dqp[3],sram_flash_data[31:24],dqp[2],sram_flash_data[23:16],dqp[1],sram_flash_data[15:8],dqp[0],sram_flash_data[7:0]}),
// Inputs
.clk (sram_clk),
.we_b (sram_flash_we_n),
.adv_lb (sram_adv_ld_n),
.ce1b (sram_ce1b),
.ce2 (sram_ce2),
.ce3b (sram_ce3b),
.oeb (sram_flash_oe_n),
.cenb (sram_cen),
.mode (sram_mode),
.bws (sram_bw),
.a (sram_a));
 
`endif // `ifdef ML501_MEMORY_SSRAM
 
 
 
`ifdef ML501_MEMORY_DDR2
 
`ifndef POST_SYNTHESIS_SIM
defparam dut.ml501_mc0.ml501_ddr2_wb_if0.ddr2_mig0.SIM_ONLY = 1;
`endif
 
always @( * ) begin
ddr2_ck_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_a_sdram <= #(TPROP_PCB_CTRL) ddr2_a_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
end // always @ ( * )
// Model delays on bi-directional BUS
genvar dqwd;
generate
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD)
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (rst_n)
);
end
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs
(
.A (ddr2_dqs_fpga[dqswd]),
.B (ddr2_dqs_sdram[dqswd]),
.reset (rst_n)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (rst_n)
);
end
endgenerate
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
 
genvar i, j;
generate
// if the data width is multiple of 16
for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs
for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen
ddr2_model u_mem0
(
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),
.cke (ddr2_cke_sdram[j]),
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
.ba (ddr2_ba_sdram),
.addr (ddr2_a_sdram),
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
.rdqs_n (),
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH])
);
end
end
endgenerate
`endif // `ifdef ML501_MEMORY_DDR2
`ifdef USE_SPI_FLASH
// SPI Flash
AT26DFxxx spi_flash
(
// Outputs
.SO (spi_flash_miso_i),
// Inputs
.CSB (spi_flash_ss_o),
.SCK (spi_flash_sclk_o),
.SI (spi_flash_mosi_o),
.WPB (spi_flash_w_n_o)
//.HOLDB (spi_flash_hold_n_o)
);
`endif // `ifdef USE_SPI_FLASH
 
initial
begin
$display("\nStarting RTL simulation of ml501 board %s test\n", `TEST_NAME_STRING);
`ifdef USE_SDRAM
$display("Using SDRAM - loading application from SPI flash memory\n");
`endif
 
`ifdef VCD
 
`ifdef ML501_MEMORY_DDR2
//#87_572_000; // DDR2 calibration completed
`endif
`ifdef USE_ETHERNET
#206_847_000 // TX Frame start in simple eth TX test
`endif
 
//#157_173_500 // Or1200 IC enabled, program begins
 
$display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
$dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
 
`ifdef VCD_DEPTH
$dumpvars(`VCD_DEPTH);
`else
$dumpvars(0);
`endif
`endif
end
 
`ifndef POST_SYNTHESIS_SIM
// Instantiate the monitor
or1200_monitor monitor();
`endif
// If we're using UART for printf output, include the
// UART decoder
`ifdef UART_PRINTF
// Define the UART's txt line for it to listen to
`define UART_TX_LINE uart0_stx_o
`define UART_BAUDRATE 115200
`include "uart_decoder.v"
`endif
 
wire ic_en = dut.i_or1k.i_or1200_top.or1200_ic_top.ic_en;
always @(posedge ic_en)
$display("Or1200 IC enabled at %t", $time);
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../rtl" "../../../../bench/verilog")
// End:
/verilog/eth_phy.v
0,0 → 1,1481
//////////////////////////////////////////////////////////////////////
//// ////
//// File name: eth_phy.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/10/18 13:58:22 tadejm
// Some code changed due to bug fixes.
//
// Revision 1.6 2002/10/09 13:16:51 tadejm
// Just back-up; not completed testbench and some testcases are not
// wotking properly yet.
//
// Revision 1.5 2002/09/18 17:55:08 tadej
// Bug repaired in eth_phy device
//
// Revision 1.3 2002/09/13 14:50:15 mohor
// Bug in MIIM fixed.
//
// Revision 1.2 2002/09/13 12:29:14 mohor
// Headers changed.
//
// Revision 1.1 2002/09/13 11:57:20 mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
//
//
 
`include "timescale.v"
`include "eth_phy_defines.v"
 
// ORPSoCv2 testbench include
// Will enable verbose if eth test
`ifdef TEST_DEFINE_FILE
`include "test_define.v"
`endif
 
 
`define MULTICAST_XFR 0
`define UNICAST_XFR 1
`define BROADCAST_XFR 2
`define UNICAST_WRONG_XFR 3
 
 
`define ETH_PHY_VERBOSE 1
 
module eth_phy // This PHY model simulate simplified Intel LXT971A PHY
(
// COMMON
m_rst_n_i,
 
// MAC TX
mtx_clk_o,
mtxd_i,
mtxen_i,
mtxerr_i,
 
// MAC RX
mrx_clk_o,
mrxd_o,
mrxdv_o,
mrxerr_o,
 
mcoll_o,
mcrs_o,
 
// MIIM
mdc_i,
md_io,
speed_o,
link_o,
duplex_o
);
 
//////////////////////////////////////////////////////////////////////
//
// Input/output signals
//
//////////////////////////////////////////////////////////////////////
 
// MAC miscellaneous signals
input m_rst_n_i;
// MAC TX signals
output mtx_clk_o;
input [3:0] mtxd_i;
input mtxen_i;
input mtxerr_i;
// MAC RX signals
output mrx_clk_o;
output [3:0] mrxd_o;
output mrxdv_o;
output mrxerr_o;
// MAC common signals
output mcoll_o;
output mcrs_o;
// MAC management signals
input mdc_i;
inout md_io;
// Sideband signals for SMII -- jb
output link_o;
output speed_o;
output duplex_o;
 
//////////////////////////////////////////////////////////////////////
//
// PHY management (MIIM) REGISTER definitions
//
//////////////////////////////////////////////////////////////////////
//
// Supported registers:
//
// Addr | Register Name
//--------------------------------------------------------------------
// 0 | Control reg. |
// 1 | Status reg. #1 |--> normal operation
// 2 | PHY ID reg. 1 |
// 3 | PHY ID reg. 2 |
//----------------------
// Addr | Data MEMORY |--> for testing
//
//--------------------------------------------------------------------
//
// Control register
reg control_bit15; // self clearing bit
reg [14:10] control_bit14_10;
reg control_bit9; // self clearing bit
reg [8:0] control_bit8_0;
// Status register
wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
wire status_bit8 = `EXTENDED_STATUS;
wire status_bit7 = 1'b0; // reserved
reg [6:0] status_bit6_0;
// PHY ID register 1
wire [15:0] phy_id1 = `PHY_ID1;
// PHY ID register 2
wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};
//--------------------------------------------------------------------
//
// Data MEMORY
reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width
//
//////////////////////////////////////////////////////////////////////
 
 
//////////////////////////////////////////////////////////////////////
//
// PHY clocks - RX & TX
//
//////////////////////////////////////////////////////////////////////
 
reg mtx_clk_o;
reg mrx_clk_o;
 
// random generator for a RX period when link is down
real rx_link_down_halfperiod;
 
always@(status_bit6_0[2])
begin
if (!status_bit6_0[2]) // Link is down
begin
#1 rx_link_down_halfperiod = ({$random} % 243) + 13;
`ifdef ETH_PHY_VERBOSE
#1 $display( " (%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!",
$time, (1000/(rx_link_down_halfperiod*2)) );
`endif
end
end
 
`ifdef ETH_PHY_VERBOSE
always@(status_bit6_0[2])
begin
if (!status_bit6_0[2]) // Link is down
#1 $display( " (%0t)(%m)Ethernet link is down!", $time);
else
#1 $display( " (%0t)(%m)Ethernet link is up!", $time);
end
`endif
 
// speed selection signal eth_speed: 1'b1 - 100 Mbps, 1'b0 - 10 Mbps
wire eth_speed;
 
assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );
 
`ifdef ETH_PHY_VERBOSE
always@(eth_speed)
begin
if (eth_speed)
#1 $display( " (%0t)(%m)PHY configured to 100 Mbps!", $time);
else
#1 $display( " (%0t)(%m)PHY configured tp 10 Mbps!", $time);
end
`endif
 
// different clock calculation between RX and TX, so that there is alsways a litle difference
/*initial
begin
set_mrx_equal_mtx = 1; // default
end*/
 
always
begin
mtx_clk_o = 0;
#7;
forever
begin
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
begin
#20 mtx_clk_o = ~mtx_clk_o;
end
else // 10 Mbps - 2.5 MHz, 400 ns
begin
#200 mtx_clk_o = ~mtx_clk_o;
end
end
end
 
always
begin
// EQUAL mrx_clk to mtx_clk
mrx_clk_o = 0;
#7;
forever
begin
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
begin
#20 mrx_clk_o = ~mrx_clk_o;
end
else // 10 Mbps - 2.5 MHz, 400 ns
begin
#200 mrx_clk_o = ~mrx_clk_o;
end
end
// DIFFERENT mrx_clk than mtx_clk
/* mrx_clk_diff_than_mtx = 1;
#3;
forever
begin
if (status_bit6_0[2]) // Link is UP
begin
if (eth_speed) // 100 Mbps - 25 MHz, 40 ns
begin
//#(((1/0.025001)/2))
#19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
end
else // 10 Mbps - 2.5 MHz, 400 ns
begin
//#(((1/0.0024999)/2))
#200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz
end
end
else // Link is down
begin
#(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz
end
end*/
// // set output mrx_clk
// if (set_mrx_equal_mtx)
// mrx_clk_o = mrx_clk_equal_to_mtx;
// else
// mrx_clk_o = mrx_clk_diff_than_mtx;
end
 
// set output mrx_clk
//assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ;
 
//////////////////////////////////////////////////////////////////////
//
// PHY management (MIIM) interface
//
//////////////////////////////////////////////////////////////////////
reg respond_to_all_phy_addr; // PHY will respond to all phy addresses
reg no_preamble; // PHY responds to frames without preamble
 
integer md_transfer_cnt; // counter countes the value of whole data transfer
reg md_transfer_cnt_reset; // for reseting the counter
reg md_io_reg; // registered input
reg md_io_output; // registered output
reg md_io_rd_wr; // op-code latched (read or write)
reg md_io_enable; // output enable
reg [4:0] phy_address; // address of PHY device
reg [4:0] reg_address; // address of a register
reg md_get_phy_address; // for shifting PHY address in
reg md_get_reg_address; // for shifting register address in
reg [15:0] reg_data_in; // data to be written in a register
reg md_get_reg_data_in; // for shifting data in
reg md_put_reg_data_in; // for storing data into a selected register
reg [15:0] reg_data_out; // data to be read from a register
reg md_put_reg_data_out; // for registering data from a selected register
 
wire [15:0] register_bus_in; // data bus to a selected register
reg [15:0] register_bus_out; // data bus from a selected register
 
initial
begin
md_io_enable = 1'b0;
respond_to_all_phy_addr = 1'b0;
no_preamble = 1'b0;
end
 
// tristate output
assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;
 
// registering input
always@(posedge mdc_i or negedge m_rst_n_i)
begin
if (!m_rst_n_i)
md_io_reg <= #1 0;
else
md_io_reg <= #1 md_io;
end
 
// getting (shifting) PHY address, Register address and Data in
// putting Data out and shifting
always@(posedge mdc_i or negedge m_rst_n_i)
begin
if (!m_rst_n_i)
begin
phy_address <= 0;
reg_address <= 0;
reg_data_in <= 0;
reg_data_out <= 0;
md_io_output <= 0;
end
else
begin
if (md_get_phy_address)
begin
phy_address[4:1] <= phy_address[3:0]; // correct address is `ETH_PHY_ADDR
phy_address[0] <= md_io;
end
if (md_get_reg_address)
begin
reg_address[4:1] <= reg_address[3:0];
reg_address[0] <= md_io;
end
if (md_get_reg_data_in)
begin
reg_data_in[15:1] <= reg_data_in[14:0];
reg_data_in[0] <= md_io;
end
if (md_put_reg_data_out)
begin
reg_data_out <= register_bus_out;
end
if (md_io_enable)
begin
md_io_output <= reg_data_out[15];
reg_data_out[15:1] <= reg_data_out[14:0];
reg_data_out[0] <= 1'b0;
end
end
end
 
assign #1 register_bus_in = reg_data_in; // md_put_reg_data_in - allows writing to a selected register
 
// counter for transfer to and from MIIM
always@(posedge mdc_i or negedge m_rst_n_i)
begin
if (!m_rst_n_i)
begin
if (no_preamble)
md_transfer_cnt <= 33;
else
md_transfer_cnt <= 1;
end
else
begin
if (md_transfer_cnt_reset)
begin
if (no_preamble)
md_transfer_cnt <= 33;
else
md_transfer_cnt <= 1;
end
else if (md_transfer_cnt < 64)
begin
md_transfer_cnt <= md_transfer_cnt + 1'b1;
end
else
begin
if (no_preamble)
md_transfer_cnt <= 33;
else
md_transfer_cnt <= 1;
end
end
end
 
// MIIM transfer control
always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or
phy_address or respond_to_all_phy_addr or no_preamble)
begin
#1;
while ((m_rst_n_i) && (md_transfer_cnt <= 64))
begin
// reset the signal - put registered data in the register (when write)
// check preamble
if (md_transfer_cnt < 33)
begin
#4 md_put_reg_data_in = 1'b0;
if (md_io_reg !== 1'b1)
begin
#1 md_transfer_cnt_reset = 1'b1;
end
else
begin
#1 md_transfer_cnt_reset = 1'b0;
end
end
 
// check start bits
else if (md_transfer_cnt == 33)
begin
if (no_preamble)
begin
#4 md_put_reg_data_in = 1'b0;
if (md_io_reg === 1'b0)
begin
#1 md_transfer_cnt_reset = 1'b0;
end
else
begin
#1 md_transfer_cnt_reset = 1'b1;
//if ((md_io_reg !== 1'bz) && (md_io_reg !== 1'b1))
if (md_io_reg !== 1'bz)
begin
// ERROR - start !
`ifdef ETH_PHY_VERBOSE
$display( "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);
`endif
#10 $stop;
end
end
end
else // with preamble
begin
#4 ;
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m)MIIM - 32-bit preamble received", $time);
`endif
// check start bit only if md_transfer_cnt_reset is inactive, because if
// preamble suppression was changed start bit should not be checked
if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))
begin
// ERROR - start !
`ifdef ETH_PHY_VERBOSE
$display( "*E (%0t)(%m)MIIM - wrong first start bit", $time);
`endif
#10 $stop;
end
end
end
 
else if (md_transfer_cnt == 34)
begin
#4;
if (md_io_reg !== 1'b1)
begin
// ERROR - start !
#1;
`ifdef ETH_PHY_VERBOSE
if (no_preamble)
$display( "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);
else
$display( "*E (%0t)(%m)MIIM - wrong second start bit", $time);
`endif
#10 $stop;
end
else
begin
`ifdef ETH_PHY_VERBOSE
if (no_preamble)
#1 $display( " (%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);
else
#1 $display( " (%0t)(%m)MIIM - 2 start bits received", $time);
`endif
end
end
 
// register the op-code (rd / wr)
else if (md_transfer_cnt == 35)
begin
#4;
if (md_io_reg === 1'b1)
begin
#1 md_io_rd_wr = 1'b1;
end
else
begin
#1 md_io_rd_wr = 1'b0;
end
end
 
else if (md_transfer_cnt == 36)
begin
#4;
if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))
begin
#1 md_io_rd_wr = 1'b1; // reading from PHY registers
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m)MIIM - op-code for READING from registers", $time);
`endif
end
else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))
begin
#1 md_io_rd_wr = 1'b0; // writing to PHY registers
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m)MIIM - op-code for WRITING to registers", $time);
`endif
end
else
begin
// ERROR - wrong opcode !
`ifdef ETH_PHY_VERBOSE
#1 $display( "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);
`endif
#10 $stop;
end
// set the signal - get PHY address
begin
#1 md_get_phy_address = 1'b1;
end
end
 
// reset the signal - get PHY address
else if (md_transfer_cnt == 41)
begin
#4 md_get_phy_address = 1'b0;
// set the signal - get register address
#1 md_get_reg_address = 1'b1;
end
 
// reset the signal - get register address
// set the signal - put register data to output register
else if (md_transfer_cnt == 46)
begin
#4 md_get_reg_address = 1'b0;
#1 md_put_reg_data_out = 1'b1;
end
 
// reset the signal - put register data to output register
// set the signal - enable md_io as output when read
else if (md_transfer_cnt == 47)
begin
#4 md_put_reg_data_out = 1'b0;
if (md_io_rd_wr) //read
begin
if (md_io_reg !== 1'bz)
begin
// ERROR - turn around !
`ifdef ETH_PHY_VERBOSE
#1 $display( "*E (%0t)(%m)MIIM - wrong turn-around cycle before reading data out", $time);
`endif
#10 $stop;
end
if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
begin
#1 md_io_enable = 1'b1;
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
`endif
end
else
begin
`ifdef ETH_PHY_VERBOSE
#1 $display( "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
`endif
end
end
else // write
begin
#1 md_io_enable = 1'b0;
// check turn around cycle when write on clock 47
if (md_io_reg !== 1'b1)
begin
// ERROR - turn around !
`ifdef ETH_PHY_VERBOSE
#1 $display( "*E (%0t)(%m)MIIM - wrong 1. turn-around cycle before writing data in",
$time);
`endif
#10 $stop;
end
end
end
 
// set the signal - get register data in when write
else if (md_transfer_cnt == 48)
begin
#4;
if (!md_io_rd_wr) // write
begin
#1 md_get_reg_data_in = 1'b1;
// check turn around cycle when write on clock 48
if (md_io_reg !== 1'b0)
begin
// ERROR - turn around !
`ifdef ETH_PHY_VERBOSE
#1 $display( "*E (%0t)(%m)MIIM - wrong 2. turn-around cycle before writing data in",
$time);
`endif
#10 $stop;
end
end
else // read
begin
#1 md_get_reg_data_in = 1'b0;
end
end
 
// reset the signal - enable md_io as output when read
// reset the signal - get register data in when write
// set the signal - put registered data in the register when write
else if (md_transfer_cnt == 64)
begin
#1 md_io_enable = 1'b0;
#4 md_get_reg_data_in = 1'b0;
if (!md_io_rd_wr) // write
begin
if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
begin
#1 md_put_reg_data_in = 1'b1;
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m)MIIM - received correct PHY ADDRESS: %x", $time, phy_address);
$display( " (%0t)(%m)MIIM - WRITING to register %x COMPLETED!", $time, reg_address);
`endif
end
else
begin
`ifdef ETH_PHY_VERBOSE
#1 $display( "*W (%0t)(%m)MIIM - received different PHY ADDRESS: %x", $time, phy_address);
$display( "*W (%0t)(%m)MIIM - NO WRITING to register %x !", $time, reg_address);
`endif
end
end
else // read
begin
`ifdef ETH_PHY_VERBOSE
if ((phy_address === `ETH_PHY_ADDR) || respond_to_all_phy_addr) // check the PHY address
#1 $display( " (%0t)(%m)MIIM - READING from register %x COMPLETED!",
$time, reg_address);
else
#1 $display( "*W (%0t)(%m)MIIM - NO READING from register %x !", $time, reg_address);
`endif
end
end
 
// wait for one clock period
@(posedge mdc_i)
#1;
end
end
 
//====================================================================
//
// PHY management (MIIM) REGISTERS
//
//====================================================================
//
// Supported registers (normal operation):
//
// Addr | Register Name
//--------------------------------------------------------------------
// 0 | Control reg.
// 1 | Status reg. #1
// 2 | PHY ID reg. 1
// 3 | PHY ID reg. 2
//----------------------
// Addr | Data MEMORY |--> for testing
//
//--------------------------------------------------------------------
//
// Control register
// reg control_bit15; // self clearing bit
// reg [14:10] control_bit14_10;
// reg control_bit9; // self clearing bit
// reg [8:0] control_bit8_0;
// Status register
// wire [15:9] status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;
// wire status_bit8 = `EXTENDED_STATUS;
// wire status_bit7 = 1'b0; // reserved
// reg [6:0] status_bit6_0 = `DEFAULT_STATUS;
// PHY ID register 1
// wire [15:0] phy_id1 = `PHY_ID1;
// PHY ID register 2
// wire [15:0] phy_id2 = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};
//--------------------------------------------------------------------
//
// Data MEMORY
// reg [15:0] data_mem [0:31]; // 32 locations of 16-bit data width
//
//====================================================================
 
//////////////////////////////////////////////////////////////////////
//
// PHY management (MIIM) REGISTER control
//
//////////////////////////////////////////////////////////////////////
 
// wholy writable registers for walking ONE's on data, phy and reg. addresses
reg registers_addr_data_test_operation;
 
// Non writable status registers
initial // always
begin
#1 status_bit6_0[6] = no_preamble;
status_bit6_0[5] = 1'b0;
status_bit6_0[3] = 1'b1;
status_bit6_0[0] = 1'b1;
end
always@(posedge mrx_clk_o)
begin
status_bit6_0[4] <= #1 1'b0;
status_bit6_0[1] <= #1 1'b0;
end
initial
begin
status_bit6_0[2] = 1'b1;
registers_addr_data_test_operation = 0;
end
 
// Reading from a selected registers
always@(reg_address or registers_addr_data_test_operation or md_put_reg_data_out or
control_bit15 or control_bit14_10 or control_bit9 or control_bit8_0 or
status_bit15_9 or status_bit8 or status_bit7 or status_bit6_0 or
phy_id1 or phy_id2)
begin
if (registers_addr_data_test_operation) // test operation
begin
if (md_put_reg_data_out) // read enable
begin
register_bus_out = #1 data_mem[reg_address];
end
end
else // normal operation
begin
if (md_put_reg_data_out) // read enable
begin
case (reg_address)
5'h0: register_bus_out = #1 {control_bit15, control_bit14_10, control_bit9, control_bit8_0};
5'h1: register_bus_out = #1 {status_bit15_9, status_bit8, status_bit7, status_bit6_0};
5'h2: register_bus_out = #1 phy_id1;
5'h3: register_bus_out = #1 phy_id2;
default: register_bus_out = #1 16'hDEAD;
endcase
end
end
end
 
// Self clear control signals
reg self_clear_d0;
reg self_clear_d1;
reg self_clear_d2;
reg self_clear_d3;
// Self clearing control
always@(posedge mdc_i or negedge m_rst_n_i)
begin
if (!m_rst_n_i)
begin
self_clear_d0 <= #1 0;
self_clear_d1 <= #1 0;
self_clear_d2 <= #1 0;
self_clear_d3 <= #1 0;
end
else
begin
self_clear_d0 <= #1 md_put_reg_data_in;
self_clear_d1 <= #1 self_clear_d0;
self_clear_d2 <= #1 self_clear_d1;
self_clear_d3 <= #1 self_clear_d2;
end
end
 
// Writing to a selected register
always@(posedge mdc_i or negedge m_rst_n_i)
begin
if ((!m_rst_n_i) || (control_bit15))
begin
if (!registers_addr_data_test_operation) // normal operation
begin
control_bit15 <= #1 0;
control_bit14_10 <= #1 {1'b0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 2'b0};
control_bit9 <= #1 0;
control_bit8_0 <= #1 {`LED_CFG3, 8'b0};
end
end
else
begin
if (registers_addr_data_test_operation) // test operation
begin
if (md_put_reg_data_in)
begin
data_mem[reg_address] <= #1 register_bus_in[15:0];
end
end
else // normal operation
begin
// bits that are normaly written
if (md_put_reg_data_in)
begin
case (reg_address)
5'h0:
begin
control_bit14_10 <= #1 register_bus_in[14:10];
control_bit8_0 <= #1 register_bus_in[8:0];
end
default:
begin
end
endcase
end
// self cleared bits written
if ((md_put_reg_data_in) && (reg_address == 5'h0))
begin
control_bit15 <= #1 register_bus_in[15];
control_bit9 <= #1 register_bus_in[9];
end
else if (self_clear_d3) // self cleared bits cleared
begin
control_bit15 <= #1 1'b0;
control_bit9 <= #1 1'b0;
end
end
end
end
 
//////////////////////////////////////////////////////////////////////
//
// PHY <-> MAC control (RX and TX clocks are at the begining)
//
//////////////////////////////////////////////////////////////////////
 
// CARRIER SENSE & COLLISION
 
// MAC common signals
reg mcoll_o;
reg mcrs_o;
// Internal signals controling Carrier sense & Collision
// MAC common signals generated when appropriate transfer
reg mcrs_rx;
reg mcrs_tx;
// delayed mtxen_i signal for generating delayed tx carrier sense
reg mtxen_d1;
reg mtxen_d2;
reg mtxen_d3;
reg mtxen_d4;
reg mtxen_d5;
reg mtxen_d6;
// collision signal set or rest within task for controling collision
reg task_mcoll;
// carrier sense signal set or rest within task for controling carrier sense
reg task_mcrs;
reg task_mcrs_lost;
// do not generate collision in half duplex - not normal operation
reg no_collision_in_half_duplex;
// generate collision in full-duplex mode also - not normal operation
reg collision_in_full_duplex;
// do not generate carrier sense in half duplex mode - not normal operation
reg no_carrier_sense_in_tx_half_duplex;
reg no_carrier_sense_in_rx_half_duplex;
// generate carrier sense during TX in full-duplex mode also - not normal operation
reg carrier_sense_in_tx_full_duplex;
// do not generate carrier sense during RX in full-duplex mode - not normal operation
reg no_carrier_sense_in_rx_full_duplex;
// on RX: delay after carrier sense signal; on TX: carrier sense delayed (delay is one clock period)
reg real_carrier_sense;
 
initial
begin
mcrs_rx = 0;
mcrs_tx = 0;
task_mcoll = 0;
task_mcrs = 0;
task_mcrs_lost = 0;
no_collision_in_half_duplex = 0;
collision_in_full_duplex = 0;
no_carrier_sense_in_tx_half_duplex = 0;
no_carrier_sense_in_rx_half_duplex = 0;
carrier_sense_in_tx_full_duplex = 0;
no_carrier_sense_in_rx_full_duplex = 0;
real_carrier_sense = 0;
end
 
// Collision
always@(m_rst_n_i or control_bit8_0 or collision_in_full_duplex or
mcrs_rx or mcrs_tx or task_mcoll or no_collision_in_half_duplex
)
begin
if (!m_rst_n_i)
mcoll_o = 0;
else
begin
if (control_bit8_0[8]) // full duplex
begin
if (collision_in_full_duplex) // collision is usually not asserted in full duplex
begin
mcoll_o = ((mcrs_rx && mcrs_tx) || task_mcoll);
`ifdef ETH_PHY_VERBOSE
if (mcrs_rx && mcrs_tx)
$display( " (%0t)(%m) Collision set in FullDuplex!", $time);
if (task_mcoll)
$display( " (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
`endif
end
else
begin
mcoll_o = task_mcoll;
`ifdef ETH_PHY_VERBOSE
if (task_mcoll)
$display( " (%0t)(%m) Collision set in FullDuplex from TASK!", $time);
`endif
end
end
else // half duplex
begin
mcoll_o = ((mcrs_rx && mcrs_tx && !no_collision_in_half_duplex) ||
task_mcoll);
`ifdef ETH_PHY_VERBOSE
if (mcrs_rx && mcrs_tx)
$display( " (%0t)(%m) Collision set in HalfDuplex!", $time);
if (task_mcoll)
$display( " (%0t)(%m) Collision set in HalfDuplex from TASK!", $time);
`endif
end
end
end
 
// Carrier sense
always@(m_rst_n_i or control_bit8_0 or carrier_sense_in_tx_full_duplex or
no_carrier_sense_in_rx_full_duplex or
no_carrier_sense_in_tx_half_duplex or
no_carrier_sense_in_rx_half_duplex or
mcrs_rx or mcrs_tx or task_mcrs or task_mcrs_lost
)
begin
if (!m_rst_n_i)
mcrs_o = 0;
else
begin
if (control_bit8_0[8]) // full duplex
begin
if (carrier_sense_in_tx_full_duplex) // carrier sense is usually not asserted during TX in full duplex
mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) ||
mcrs_tx || task_mcrs) && !task_mcrs_lost;
else
mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_full_duplex) ||
task_mcrs) && !task_mcrs_lost;
end
else // half duplex
begin
mcrs_o = ((mcrs_rx && !no_carrier_sense_in_rx_half_duplex) ||
(mcrs_tx && !no_carrier_sense_in_tx_half_duplex) ||
task_mcrs) && !task_mcrs_lost;
end
end
end
 
// MAC TX CONTROL (RECEIVING AT PHY)
 
// storage memory for TX data received from MAC
reg [7:0] tx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width
reg [31:0] tx_mem_addr_in; // address for storing to TX memory
reg [7:0] tx_mem_data_in; // data for storing to TX memory
reg [31:0] tx_cnt; // counts nibbles
 
// control data of a TX packet for upper layer of testbench
reg tx_preamble_ok;
reg tx_sfd_ok;
// if there is a drible nibble, then tx packet is not byte aligned!
reg tx_byte_aligned_ok;
// complete length of TX packet (Bytes) received (without preamble and SFD)
reg [31:0] tx_len;
// complete length of TX packet (Bytes) received (without preamble and SFD) untill MTxErr signal was set first
reg [31:0] tx_len_err;
 
// TX control
always@(posedge mtx_clk_o)
begin
// storing data and basic checking of frame
if (!m_rst_n_i)
begin
tx_cnt <= 0;
tx_preamble_ok <= 0;
tx_sfd_ok <= 0;
tx_len <= 0;
tx_len_err <= 0;
end
else
begin
if (!mtxen_i)
begin
tx_cnt <= 0;
end
else
begin
// tx nibble counter
tx_cnt <= tx_cnt + 1;
// set initial values and check first preamble nibble
if (tx_cnt == 0)
begin
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m) TX frame started with tx_en set!", $time);
`endif
if (mtxd_i == 4'h5)
tx_preamble_ok <= 1;
else
tx_preamble_ok <= 0;
tx_sfd_ok <= 0;
tx_byte_aligned_ok <= 0;
tx_len <= 0;
tx_len_err <= 0;
// tx_mem_addr_in <= 0;
end
 
// check preamble
if ((tx_cnt > 0) && (tx_cnt <= 13))
begin
if ((tx_preamble_ok != 1) || (mtxd_i != 4'h5))
tx_preamble_ok <= 0;
end
// check SFD
if (tx_cnt == 14)
begin
`ifdef ETH_PHY_VERBOSE
if (tx_preamble_ok == 1)
$display( " (%0t)(%m) TX frame preamble OK!", $time);
else
$display( "*E (%0t)(%m) TX frame preamble NOT OK!", $time);
`endif
if (mtxd_i == 4'h5)
tx_sfd_ok <= 1;
else
tx_sfd_ok <= 0;
end
if (tx_cnt == 15)
begin
if ((tx_sfd_ok != 1) || (mtxd_i != 4'hD))
tx_sfd_ok <= 0;
end
 
// control for storing addresses, type/length, data and FCS to TX memory
if (tx_cnt > 15)
begin
if (tx_cnt == 16)
begin
`ifdef ETH_PHY_VERBOSE
if (tx_sfd_ok == 1)
$display( " (%0t)(%m) TX frame SFD OK!", $time);
else
$display( "*E (%0t)(%m) TX frame SFD NOT OK!", $time);
`endif
end
 
if (tx_cnt[0] == 0)
begin
tx_mem_data_in[3:0] <= mtxd_i; // storing LSB nibble
tx_byte_aligned_ok <= 0; // if transfer will stop after this, then there was drible nibble
end
else
begin
tx_mem[tx_mem_addr_in[21:0]] <= {mtxd_i, tx_mem_data_in[3:0]}; // storing data into tx memory
tx_len <= tx_len + 1; // enlarge byte length counter
tx_byte_aligned_ok <= 1; // if transfer will stop after this, then transfer is byte alligned
tx_mem_addr_in <= tx_mem_addr_in + 1'b1;
end
 
if (mtxerr_i)
tx_len_err <= tx_len;
end
end
end
 
// generating CARRIER SENSE for TX with or without delay
if (!m_rst_n_i)
begin
mcrs_tx <= 0;
mtxen_d1 <= 0;
mtxen_d2 <= 0;
mtxen_d3 <= 0;
mtxen_d4 <= 0;
mtxen_d5 <= 0;
mtxen_d6 <= 0;
end
else
begin
mtxen_d1 <= mtxen_i;
mtxen_d2 <= mtxen_d1;
mtxen_d3 <= mtxen_d2;
mtxen_d4 <= mtxen_d3;
mtxen_d5 <= mtxen_d4;
mtxen_d6 <= mtxen_d5;
if (real_carrier_sense)
mcrs_tx <= mtxen_d6;
else
mcrs_tx <= mtxen_i;
end
end
 
`ifdef ETH_PHY_VERBOSE
reg frame_started;
 
initial
begin
frame_started = 0;
end
always@(posedge mtxen_i)
begin
frame_started <= 1;
end
always@(negedge mtxen_i)
begin
if (frame_started)
begin
$display( " (%0t)(%m) TX frame ended with tx_en reset!", $time);
frame_started <= 0;
end
end
 
always@(posedge mrxerr_o)
begin
$display( " (%0t)(%m) RX frame ERROR signal was set!", $time);
end
`endif
 
//////////////////////////////////////////////////////////////////////
//
// Tasks for PHY <-> MAC transactions
//
//////////////////////////////////////////////////////////////////////
 
initial
begin
tx_mem_addr_in = 0;
end
 
// setting the address of tx_mem, to set the starting point of tx packet
task set_tx_mem_addr;
input [31:0] tx_mem_address;
begin
#1 tx_mem_addr_in = tx_mem_address;
end
endtask // set_tx_mem_addr
 
// storage memory for RX data to be transmited to MAC
reg [7:0] rx_mem [0:4194303]; // 4194304 locations (22 address lines) of 8-bit data width
 
// MAC RX signals
reg [3:0] mrxd_o;
reg mrxdv_o;
reg mrxerr_o;
 
initial
begin
mrxd_o = 0;
mrxdv_o = 0;
mrxerr_o = 0;
mcrs_rx = 0;
end
 
task send_rx_packet;
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
input [31:0] start_addr; // start address
input [31:0] len; // length of frame in Bytes (without preamble and SFD)
input plus_drible_nibble; // if length is longer for one nibble
integer rx_cnt;
reg [31:0] rx_mem_addr_in; // address for reading from RX memory
reg [7:0] rx_mem_data_out; // data for reading from RX memory
begin
@(posedge mrx_clk_o);
// generating CARRIER SENSE for TX with or without delay
if (real_carrier_sense)
#1 mcrs_rx = 1;
else
#1 mcrs_rx = 0;
@(posedge mrx_clk_o);
#1 mcrs_rx = 1;
#1 mrxdv_o = 1;
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m) RX frame started with rx_dv set!", $time);
`endif
// set initial rx memory address
rx_mem_addr_in = start_addr;
// send preamble
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
begin
#1 mrxd_o = preamble_data[3:0];
#1 preamble_data = preamble_data >> 4;
@(posedge mrx_clk_o);
end
// send SFD
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
begin
#1 mrxd_o = sfd_data[3:0];
#1 sfd_data = sfd_data >> 4;
@(posedge mrx_clk_o);
end
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m) RX frame preamble and SFD sent!", $time);
`endif
// send packet's addresses, type/length, data and FCS
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
begin
#1;
rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
mrxd_o = rx_mem_data_out[3:0];
@(posedge mrx_clk_o);
#1;
mrxd_o = rx_mem_data_out[7:4];
rx_mem_addr_in = rx_mem_addr_in + 1;
@(posedge mrx_clk_o);
#1;
end
if (plus_drible_nibble)
begin
rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
mrxd_o = rx_mem_data_out[3:0];
@(posedge mrx_clk_o);
end
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
`endif
#1 mcrs_rx = 0;
#1 mrxdv_o = 0;
@(posedge mrx_clk_o);
`ifdef ETH_PHY_VERBOSE
$display( " (%0t)(%m) RX frame ended with rx_dv reset!", $time);
`endif
end
endtask // send_rx_packet
 
 
 
task GetDataOnMRxD;
input [15:0] Len;
input [31:0] TransferType;
integer tt;
 
begin
@ (posedge mrx_clk_o);
#1 mrxdv_o=1'b1;
 
for(tt=0; tt<15; tt=tt+1)
begin
mrxd_o=4'h5; // preamble
@ (posedge mrx_clk_o);
#1;
end
 
mrxd_o=4'hd; // SFD
 
for(tt=1; tt<(Len+1); tt=tt+1)
begin
@ (posedge mrx_clk_o);
#1;
if(TransferType == `UNICAST_XFR && tt == 1)
mrxd_o = 4'h0; // Unicast transfer
else if(TransferType == `BROADCAST_XFR && tt < 7)
mrxd_o = 4'hf;
else
mrxd_o = tt[3:0]; // Multicast transfer
 
@ (posedge mrx_clk_o);
#1;
 
if(TransferType == `BROADCAST_XFR && tt == 6)
mrxd_o = 4'he;
else
 
if(TransferType == `BROADCAST_XFR && tt < 7)
mrxd_o = 4'hf;
else
mrxd_o = tt[7:4];
end
 
@ (posedge mrx_clk_o);
#1;
mrxdv_o = 1'b0;
end
endtask // GetDataOnMRxD
 
 
//////////////////////////////////////////////////////////////////////
//
// Tastks for controling PHY statuses and rx error
//
//////////////////////////////////////////////////////////////////////
 
// Link control tasks
task link_up_down;
input test_op;
begin
#1 status_bit6_0[2] = test_op; // 1 - link up; 0 - link down
end
endtask
 
// RX error
task rx_err;
input test_op;
begin
#1 mrxerr_o = test_op; // 1 - RX error set; 0 - RX error reset
end
endtask
 
//////////////////////////////////////////////////////////////////////
//
// Tastks for controling PHY carrier sense and collision
//
//////////////////////////////////////////////////////////////////////
 
// Collision
task collision;
input test_op;
begin
#1 task_mcoll = test_op;
end
endtask
 
// Carrier sense
task carrier_sense;
input test_op;
begin
#1 task_mcrs = test_op;
end
endtask
 
// Carrier sense lost - higher priority than Carrier sense task
task carrier_sense_lost;
input test_op;
begin
#1 task_mcrs_lost = test_op;
end
endtask
 
// No collision detection in half duplex
task no_collision_hd_detect;
input test_op;
begin
#1 no_collision_in_half_duplex = test_op;
end
endtask
 
// Collision detection in full duplex also
task collision_fd_detect;
input test_op;
begin
#1 collision_in_full_duplex = test_op;
end
endtask
 
// No carrier sense detection at TX in half duplex
task no_carrier_sense_tx_hd_detect;
input test_op;
begin
#1 no_carrier_sense_in_tx_half_duplex = test_op;
end
endtask
 
// No carrier sense detection at RX in half duplex
task no_carrier_sense_rx_hd_detect;
input test_op;
begin
#1 no_carrier_sense_in_rx_half_duplex = test_op;
end
endtask
 
// Carrier sense detection at TX in full duplex also
task carrier_sense_tx_fd_detect;
input test_op;
begin
#1 carrier_sense_in_tx_full_duplex = test_op;
end
endtask
 
// No carrier sense detection at RX in full duplex
task no_carrier_sense_rx_fd_detect;
input test_op;
begin
#1 no_carrier_sense_in_rx_full_duplex = test_op;
end
endtask
 
// Set real delay on carrier sense signal (and therefor collision signal)
task carrier_sense_real_delay;
input test_op;
begin
#1 real_carrier_sense = test_op;
end
endtask
 
//////////////////////////////////////////////////////////////////////
//
// Tastks for controling PHY management test operation
//
//////////////////////////////////////////////////////////////////////
 
// Set registers to test operation and respond to all phy addresses
task test_regs;
input test_op;
begin
#1 registers_addr_data_test_operation = test_op;
respond_to_all_phy_addr = test_op;
end
endtask
 
// Clears data memory for testing the MII
task clear_test_regs;
integer i;
begin
for (i = 0; i < 32; i = i + 1)
begin
#1 data_mem[i] = 16'h0;
end
end
endtask
 
// Accept frames with preamble suppresed
task preamble_suppresed;
input test_op;
begin
#1 no_preamble = test_op;
md_transfer_cnt_reset = 1'b1;
@(posedge mdc_i);
#1 md_transfer_cnt_reset = 1'b0;
end
endtask
 
 
 
// Sideband signals for external SMII converter --jb
assign link_o = status_bit6_0[2];
assign speed_o = eth_speed;
assign duplex_o = control_bit8_0[8];
 
 
 
 
endmodule
 
/verilog/cy7c1354.v
0,0 → 1,482
//************************************************************************
//************************************************************************
//** This model is the property of Cypress Semiconductor Corp and is **
//** protected by the US copyright laws, any unauthorized copying and **
//** distribution is prohibited. Cypress reserves the right to change **
//** any of the functional specifications without any prior notice. **
//** Cypress is not liable for any damages which may result from the **
//** use of this functional model. **
//** **
//** File Name : CY7C1354B **
//** **
//** Revision : 1.1 - 01/30/2004 **
//** **
//** The timings are to be selected by the user depending upon the **
//** frequency of operation from the datasheet. **
//** **
//** Model : CY7C1354B - 256K x 36 NoBL Pipelined SRAM **
//** Queries : MPD Applications **
//** e-mail: mpd_apps@cypress.com **
//************************************************************************
//************************************************************************
 
`timescale 1ns / 10ps
 
// NOTE : Any setup/hold errors will force input signal to x state
// or if results indeterminant (write addr) core is reset x
 
// define fixed values
 
`define wordsize (36 -1) //
`define no_words (262144 -1) // 256K x 36 RAM
 
module cy7c1354 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
 
inout [`wordsize:0] d;
input clk, // clock input (R)
we_b, // byte write enable(L)
adv_lb, // burst(H)/load(L) address
ce1b, // chip enable(L)
ce2, // chip enable(H)
ce3b, // chip enable(L)
oeb, // async output enable(L)(read)
cenb, // clock enable(L)
mode; // interleave(H)/linear(L) burst
input [3:0] bws; // byte write select(L)
input [18:0] a; // address bus
 
// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK ***
// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT ***
 
//**********************************************************************
// This model is configured for 166 MHz Operation (CY7C1354-166).
//**********************************************************************
`define teohz #3.5
`define teolz #0
`define tchz #3.5
`define tclz #1.5
`define tco #3.5
`define tdoh #1.5
 
`define tas 1.5
`define tah 0.5
 
/**********************************************************************
// Timings for 225MHz
//**********************************************************************
`define teohz #2.8
`define teolz #0
`define tchz #2.8
`define tclz #1.5
`define tco #2.8
`define tdoh #1.5
 
`define tas 1.5
`define tah 0.5
 
//***********************************************************************
// Timings for 200MHz
//**********************************************************************
`define teohz #3.2
`define teolz #0
`define tchz #3.2
`define tclz #1.5
`define tco #3.2
`define tdoh #1.5
 
`define tas 1.5
`define tah 0.5
***********************************************************************/
 
reg notifier; // error support reg's
reg noti1_0;
reg noti1_1;
reg noti1_2;
reg noti1_3;
reg noti1_4;
reg noti1_5;
reg noti1_6;
reg noti2;
 
 
wire chipen; // combined chip enable (high for an active chip)
 
reg chipen_d; // _d = delayed
reg chipen_o; // _o = operational = delayed sig or _d sig
 
wire writestate; // holds 1 if any of writebus is low
reg writestate_d;
reg writestate_o;
 
wire loadcyc; // holds 1 for load cycles (setup and hold checks)
wire writecyc; // holds 1 for write cycles (setup and hold checks)
wire [3:0] bws; // holds the bws values
 
wire [3:0] writebusb; // holds the "internal" bws bus based on we_b
reg [3:0] writebusb_d;
reg [3:0] writebusb_o;
 
wire [2:0] operation; // holds chipen, adv_ld and writestate
reg [2:0] operation_d;
reg [2:0] operation_o;
 
wire [17:0] a; // address input bus
reg [17:0] a_d;
reg [17:0] a_o;
 
reg [`wordsize:0] do; // data output reg
reg [`wordsize:0] di; // data input bus
reg [`wordsize:0] dd; // data delayed bus
 
wire tristate; // tristate output (on a bytewise basis) when asserted
reg cetri; // register set by chip disable which sets the tristate
reg oetri; // register set by oe which sets the tristate
reg enable; // register to make the ram enabled when equal to 1
reg [17:0] addreg; // register to hold the input address
reg [`wordsize:0] pipereg; // register for the output data
 
reg [`wordsize:0] mem [0:`no_words]; // RAM array
 
reg [`wordsize:0] writeword; // temporary holding register for the write data
reg burstinit; // register to hold a[0] for burst type
reg [18:0] i; // temporary register used to write to all mem locs.
reg writetri; // tristate
reg lw, bw; // pipelined write functions
reg we_bl;
 
 
wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 36'bz ; // data bus
 
assign chipen = (adv_lb == 1 ) ? chipen_d :
~ce1b & ce2 & ~ce3b ;
 
assign writestate = ~& writebusb;
 
assign operation = {chipen, adv_lb, writestate};
 
assign writebusb[3:0] = ( we_b ==0 & adv_lb ==0) ? bws[3:0]:
( we_b ==1 & adv_lb ==0) ? 4'b1111 :
( we_bl ==0 & adv_lb ==1) ? bws[3:0]:
( we_bl ==1 & adv_lb ==1) ? 4'b1111 :
4'bxxxx ;
 
assign loadcyc = chipen & !cenb;
 
assign writecyc = writestate_d & enable & ~cenb & chipen; // check
 
assign tristate = cetri | writetri | oetri;
 
pullup (mode);
 
// formers for notices/errors etc
//
//$display("NOTICE : xxx :");
//$display("WARNING : xxx :");
//$display("ERROR *** : xxx :");
 
 
// initialize the output to be tri-state, ram to be disabled
 
initial
begin
// signals
 
writetri = 0;
cetri = 1;
enable = 0;
lw = 0;
bw = 0;
 
// error signals
 
notifier = 0;
noti1_0 = 0;
noti1_1 = 0;
noti1_2 = 0;
noti1_3 = 0;
noti1_4 = 0;
noti1_5 = 0;
noti1_6 = 0;
noti2 = 0;
 
end
 
 
 
// asynchronous OE
 
always @(oeb)
begin
if (oeb == 1)
oetri <= `teohz 1;
else
oetri <= `teolz 0;
end
 
// *** SETUP / HOLD VIOLATIONS ***
 
always @(noti2)
begin
$display("NOTICE : 020 : Data bus corruption");
force d =36'bx;
#1;
release d;
end
 
always @(noti1_0)
begin
$display("NOTICE : 010 : Byte write corruption");
force bws = 4'bx;
#1;
release bws;
end
 
always @(noti1_1)
begin
$display("NOTICE : 011 : Byte enable corruption");
force we_b = 1'bx;
#1;
release we_b;
end
 
always @(noti1_2)
begin
$display("NOTICE : 012 : CE1B corruption");
force ce1b =1'bx;
#1;
release ce1b;
end
 
always @(noti1_3)
begin
$display("NOTICE : 013 : CE2 corruption");
force ce2 =1'bx;
#1;
release ce2;
end
 
always @(noti1_4)
begin
$display("NOTICE : 014 : CE3B corruption");
force ce3b =1'bx;
#1;
release ce3b;
end
 
always @(noti1_5)
begin
$display("NOTICE : 015 : CENB corruption");
force cenb =1'bx;
#1;
release cenb;
end
 
always @(noti1_6)
begin
$display("NOTICE : 016 : ADV_LB corruption");
force adv_lb = 1'bx;
#1;
release adv_lb;
end
 
// synchronous functions from clk edge
 
always @(posedge clk)
if (!cenb)
begin
#0.01;
// latch conditions on adv_lb
 
if (adv_lb)
we_bl <= we_bl;
else
we_bl <= we_b;
 
chipen_d <= chipen;
 
chipen_o <= chipen;
writestate_o <= writestate;
writestate_d <= writestate_o;
writebusb_o <= writebusb;
writebusb_d <= writebusb_o;
operation_o <= operation;
a_o <= a;
a_d <= a_o;
di = d;
 
// execute previously pipelined fns
 
if (lw) begin
loadwrite;
lw =0;
end
 
if (bw) begin
burstwrite;
bw =0;
end
 
// decode input/piplined state
 
casex (operation_o)
3'b0?? : turnoff;
3'b101 : setlw;
3'b111 : setbw;
3'b100 : loadread;
3'b110 : burstread;
default : unknown; // output unknown values and display an error message
endcase
 
do <= `tco pipereg;
 
end
 
// *** task section ***
 
task read;
begin
if (enable) cetri <= `tclz 0;
do <= `tdoh 36'hx;
writetri <= `tchz 0;
pipereg = mem[addreg];
end
endtask
 
task write;
begin
if (enable) cetri <= `tclz 0;
writeword = mem[addreg]; // set up a word to hold the data for the current location
/* overwrite the current word for the bytes being written to */
if (!writebusb_d[3]) writeword[35:27] = di[35:27];
if (!writebusb_d[2]) writeword[26:18] = di[26:18];
if (!writebusb_d[1]) writeword[17:9] = di[17:9];
if (!writebusb_d[0]) writeword[8:0] = di[8:0];
writeword = writeword & writeword; //convert z to x states
mem[addreg] = writeword; // store the new word into the memory location
//writetri <= `tchz 1; // tristate the outputs
end
endtask
 
task setlw;
begin
lw =1;
writetri <= `tchz 1; // tristate the outputs
end
endtask
 
task setbw;
begin
bw =1;
writetri <= `tchz 1; // tristate the outputs
end
endtask
 
task loadread;
begin
burstinit = a_o[0];
addreg = a_o;
enable = 1;
read;
end
endtask
 
task loadwrite;
begin
burstinit = a_d[0];
addreg = a_d;
enable = 1;
write;
end
endtask
 
task burstread;
begin
burst;
read;
end
endtask
 
task burstwrite;
begin
burst;
write;
end
endtask
 
task unknown;
begin
do = 36'bx;
// $display ("Unknown function: Operation = %b\n", operation);
end
endtask
 
task turnoff;
begin
enable = 0;
cetri <= `tchz 1;
pipereg = 36'h0;
end
endtask
 
task burst;
begin
if (burstinit == 0 || mode == 0)
begin
case (addreg[1:0])
2'b00: addreg[1:0] = 2'b01;
2'b01: addreg[1:0] = 2'b10;
2'b10: addreg[1:0] = 2'b11;
2'b11: addreg[1:0] = 2'b00;
default: addreg[1:0] = 2'bxx;
endcase
end
else
begin
case (addreg[1:0])
2'b00: addreg[1:0] = 2'b11;
2'b01: addreg[1:0] = 2'b00;
2'b10: addreg[1:0] = 2'b01;
2'b11: addreg[1:0] = 2'b10;
default: addreg[1:0] = 2'bxx;
endcase
end
end
endtask
 
// IO checks
 
specify
// specify the setup and hold checks
 
// notifier will wipe memory as result is indeterminent
 
$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);
 
// noti1 should make ip = 'bx;
 
$setuphold(posedge clk, bws, `tas, `tah, noti1_0);
 
$setuphold(posedge clk, we_b, `tas, `tah, noti1_1);
$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);
$setuphold(posedge clk, ce2, `tas, `tah, noti1_3);
$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);
 
// noti2 should make d = 36'hxxxxxxxxx;
 
$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);
//$setuphold(posedge clk &&& WriteTimingCheck , d, `tas, `tah, noti2);
 
// add extra tests here.
 
$setuphold(posedge clk, cenb, `tas, `tah, noti1_5);
$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);
 
endspecify
 
endmodule
 
 
/verilog/WireDelay.v
0,0 → 1,123
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2008/12/23 14:26:00 $
// \ \ / \ Date Created : Thu Feb 21 2008
// \___\/\___\
//
// Device : Virtex-5
// Design Name : DDR2
// Description: This module provide
// the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
 
// The model is sensitive to transactions on all ports. Once a
// transaction is detected, all other transactions are ignored
// for that simulation time (i.e. further transactions in that
// delta time are ignored).
//
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//*****************************************************************************
 
`timescale 1ns / 1ps
 
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0
)
(
inout A,
inout B,
input reset
);
 
reg A_r;
reg B_r;
reg line_en;
 
assign A = A_r;
assign B = B_r;
 
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
A_r <= #Delay_rd B;
B_r <= 1'bz;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
 
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
/verilog/ml501_testbench_defines.v
0,0 → 1,60
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC on Xilinx ml501 Testbench Defines ////
//// ////
//// Description ////
//// ORPSoC testbench defines file ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// 100MHz board clock
// Is an FPGA-targetted sim for Xilinx stuff, meaning we'll be including
// glbl.v, meaning timescale will be 1ps/1ps, so clock period must be in ps
`define CLOCK_PERIOD 10_000
`define CLOCK_RATE 100_000_000
 
// Period for 125MHz clock is 8ns
`define ETH_CLK_PERIOD 8
 
// The ORPSoC tests makefile should generate the test_define.v file in
// the sim/run directory.
`ifdef TEST_DEFINE_FILE
`include "test_define.v"
`else
`define TEST_NAME_STRING "unspecified-test"
`define TEST_RESULTS_DIR "./"
`endif
 
`undef UART_LOG_TX

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