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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
- from Rev 412 to Rev 415
- ↔ Reverse comparison
Rev 412 → Rev 415
/verilog/include/eth_stim.v
451,6 → 451,137
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`ifdef XILINX_DDR2 |
// Gets word from correct bank |
task get_32bitword_from_xilinx_ddr2; |
input [31:0] addr; |
output [31:0] insn; |
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2, |
ddr2_array_line3; |
integer word_in_line_num; |
begin |
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), |
// 16 words total |
gen_cs[0].gen[0].u_mem0.memory_read(addr[28:27],addr[26:13], |
{addr[12:6],3'd0}, |
ddr2_array_line0); |
gen_cs[0].gen[1].u_mem0.memory_read(addr[28:27],addr[26:13], |
{addr[12:6],3'd0}, |
ddr2_array_line1); |
gen_cs[0].gen[2].u_mem0.memory_read(addr[28:27],addr[26:13], |
{addr[12:6],3'd0}, |
ddr2_array_line2); |
gen_cs[0].gen[3].u_mem0.memory_read(addr[28:27],addr[26:13], |
{addr[12:6],3'd0}, |
ddr2_array_line3); |
case (addr[5:2]) |
4'h0: |
begin |
insn[15:0] = ddr2_array_line0[15:0]; |
insn[31:16] = ddr2_array_line1[15:0]; |
end |
4'h1: |
begin |
insn[15:0] = ddr2_array_line2[15:0]; |
insn[31:16] = ddr2_array_line3[15:0]; |
end |
4'h2: |
begin |
insn[15:0] = ddr2_array_line0[31:16]; |
insn[31:16] = ddr2_array_line1[31:16]; |
end |
4'h3: |
begin |
insn[15:0] = ddr2_array_line2[31:16]; |
insn[31:16] = ddr2_array_line3[31:16]; |
end |
4'h4: |
begin |
insn[15:0] = ddr2_array_line0[47:32]; |
insn[31:16] = ddr2_array_line1[47:32]; |
end |
4'h5: |
begin |
insn[15:0] = ddr2_array_line2[47:32]; |
insn[31:16] = ddr2_array_line3[47:32]; |
end |
4'h6: |
begin |
insn[15:0] = ddr2_array_line0[63:48]; |
insn[31:16] = ddr2_array_line1[63:48]; |
end |
4'h7: |
begin |
insn[15:0] = ddr2_array_line2[63:48]; |
insn[31:16] = ddr2_array_line3[63:48]; |
end |
4'h8: |
begin |
insn[15:0] = ddr2_array_line0[79:64]; |
insn[31:16] = ddr2_array_line1[79:64]; |
end |
4'h9: |
begin |
insn[15:0] = ddr2_array_line2[79:64]; |
insn[31:16] = ddr2_array_line3[79:64]; |
end |
4'ha: |
begin |
insn[15:0] = ddr2_array_line0[95:80]; |
insn[31:16] = ddr2_array_line1[95:80]; |
end |
4'hb: |
begin |
insn[15:0] = ddr2_array_line2[95:80]; |
insn[31:16] = ddr2_array_line3[95:80]; |
end |
4'hc: |
begin |
insn[15:0] = ddr2_array_line0[111:96]; |
insn[31:16] = ddr2_array_line1[111:96]; |
end |
4'hd: |
begin |
insn[15:0] = ddr2_array_line2[111:96]; |
insn[31:16] = ddr2_array_line3[111:96]; |
end |
4'he: |
begin |
insn[15:0] = ddr2_array_line0[127:112]; |
insn[31:16] = ddr2_array_line1[127:112]; |
end |
4'hf: |
begin |
insn[15:0] = ddr2_array_line2[127:112]; |
insn[31:16] = ddr2_array_line3[127:112]; |
end |
endcase // case (addr[5:2]) |
end |
endtask |
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task get_byte_from_xilinx_ddr2; |
input [31:0] addr; |
output [7:0] data_byte; |
reg [31:0] word; |
begin |
get_32bitword_from_xilinx_ddr2(addr, word); |
case (addr[1:0]) |
2'b00: |
data_byte = word[31:24]; |
2'b01: |
data_byte = word[23:16]; |
2'b10: |
data_byte = word[15:8]; |
2'b11: |
data_byte = word[7:0]; |
endcase // case (addr[1:0]) |
end |
endtask // get_byte_from_xilinx_ddr2 |
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`endif |
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// |
// Check packet TX'd by MAC was good |
// |
496,13 → 627,29
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// Variable we'll use for index in the PHY's TX buffer |
buffer = 0; // Start of TX data |
`ifdef VERSATILE_SDRAM |
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for (i=0;i<tx_len_bd;i=i+1) |
begin |
//$display("Checking address in tx bd 0x%0h",txpnt_sdram); |
sdram_byte = 8'hx; |
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sdram0.get_byte(txpnt_sdram,sdram_byte); |
`ifdef VERSATILE_SDRAM |
sdram0.get_byte(txpnt_sdram,sdram_byte); |
`endif |
`ifdef XILINX_DDR2 |
get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte); |
`endif |
if (sdram_byte === 8'hx) |
begin |
$display(" * Error: sdram_byte was %x", sdram_byte); |
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$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx"); |
$display(" * RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h", |
tx_bd_addr, txpnt_wb); |
$finish; |
end |
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phy_byte = eth_phy0.tx_mem[buffer]; |
// Debugging output |
//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte); |
519,12 → 666,6
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end // for (i=0;i<tx_len_bd;i=i+1) |
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`else |
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!"); |
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h", |
tx_bd_addr, txpnt_wb); |
$finish; |
`endif // !`ifdef VERSATILE_SDRAM |
if (failure) |
begin |
#100 |
1002,14 → 1143,8
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rxpnt_wb = {14'd0,rx_bd_addr[17:0]}; |
rxpnt_sdram = rx_bd_addr[24:0]; |
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`ifdef VERSATILE_SDRAM |
// We'll look inside the SDRAM array |
// Hard coded for the SDRAM buffer area to be from the halfway mark in |
// memory (so starting in Bank2) |
// We'll be passed the offset from the beginning of the buffer area |
// in rxpnt_wb. This value will be in bytes. |
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//$display("RAM pointer for BD is 0x%h, SDRAM addr is 0x%h", rx_bd_addr, rxpnt_sdram); |
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1016,7 → 1151,22
for (i=0;i<len;i=i+1) |
begin |
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sdram0.get_byte(rxpnt_sdram,sdram_byte); |
sdram_byte = 8'hx; |
`ifdef VERSATILE_SDRAM |
sdram0.get_byte(rxpnt_sdram,sdram_byte); |
`endif |
`ifdef XILINX_DDR2 |
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte); |
`endif |
if (sdram_byte === 8'hx) |
begin |
$display(" * Error:"); |
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$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx"); |
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h", |
rx_bd_addr, rxpnt_wb); |
$finish; |
end |
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phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer]; |
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1034,16 → 1184,7
rxpnt_sdram = rxpnt_sdram+1; |
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end // for (i=0;i<len;i=i+2) |
`else |
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$display("SET ME UP TO LOOK IN ANOTHER MEMORY!"); |
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h", |
rx_bd_addr, rxpnt_wb); |
$finish; |
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`endif // !`ifdef VERSATILE_SDRAM |
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if (failure) |
begin |
#100 |
/verilog/include/ddr2_model_preload.v
53,4 → 53,4
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end // for (ram_ptr = 0 ; ram_ptr < ... |
$display("(%t) * DDR2 RAM %1d preloaded",$time, i); |
end // initial begin |
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/verilog/orpsoc_testbench.v
73,14 → 73,14
tri1 i2c_scl, i2c_sda; |
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`ifdef JTAG_DEBUG |
wire tdo_pad_o; |
wire tck_pad_i; |
wire tms_pad_i; |
wire tdi_pad_i; |
wire tdo_pad_o; |
wire tck_pad_i; |
wire tms_pad_i; |
wire tdi_pad_i; |
`endif |
`ifdef UART0 |
wire uart0_stx_pad_o; |
wire uart0_srx_pad_i; |
wire uart0_stx_pad_o; |
wire uart0_srx_pad_i; |
`endif |
`ifdef GPIO0 |
wire [gpio0_io_width-1:0] gpio0_io; |
151,16 → 151,16
wire [ODT_WIDTH-1:0] ddr2_odt_fpga; |
`endif |
`ifdef XILINX_SSRAM |
wire sram_clk; |
wire sram_clk_fb; |
wire sram_adv_ld_n; |
wire [3:0] sram_bw; |
wire sram_cen; |
wire [21:1] sram_flash_addr; |
wire [31:0] sram_flash_data; |
wire sram_flash_oe_n; |
wire sram_flash_we_n; |
wire sram_mode; |
wire sram_clk; |
wire sram_clk_fb; |
wire sram_adv_ld_n; |
wire [3:0] sram_bw; |
wire sram_cen; |
wire [21:1] sram_flash_addr; |
wire [31:0] sram_flash_data; |
wire sram_flash_oe_n; |
wire sram_flash_we_n; |
wire sram_mode; |
`endif |
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orpsoc_top dut |
206,9 → 206,12
.uart0_srx_expheader_pad_i (uart0_srx_pad_i), |
`endif |
`ifdef SPI0 |
.spi0_sck_o (spi0_sck_o), |
/* |
via STARTUP_VIRTEX5 |
.spi0_sck_o (spi0_sck_o), |
.spi0_miso_i (spi0_miso_i), |
*/ |
.spi0_mosi_o (spi0_mosi_o), |
.spi0_miso_i (spi0_miso_i), |
.spi0_ss_o (spi0_ss_o), |
`endif |
`ifdef I2C0 |
252,11 → 255,11
`ifndef SIM_QUIET |
`define CPU_ic_top or1200_ic_top |
`define CPU_dc_top or1200_dc_top |
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en; |
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en; |
always @(posedge ic_en) |
$display("Or1200 IC enabled at %t", $time); |
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wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en; |
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en; |
always @(posedge dc_en) |
$display("Or1200 DC enabled at %t", $time); |
`endif |
281,8 → 284,15
`endif // `ifdef JTAG_DEBUG |
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`ifdef SPI0 |
// STARTUP_VIRTEX5 module routes these out on the board. |
// So for now just connect directly to the internals here. |
assign spi0_sck_o = dut.spi0_sck_o; |
assign dut.spi0_miso_i = spi0_miso_i; |
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// SPI flash memory - M25P16 compatible SPI protocol |
AT26DFxxx spi0_flash |
AT26DFxxx |
#(.MEMSIZE(2048*1024)) // 2MB flash on ML501 |
spi0_flash |
(// Outputs |
.SO (spi0_miso_i), |
// Inputs |
291,6 → 301,8
.SI (spi0_mosi_o), |
.WPB (1'b1) |
); |
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`endif // `ifdef SPI0 |
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`ifdef ETH0 |
331,11 → 343,11
`endif // `ifdef ETH0 |
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`ifdef XILINX_SSRAM |
wire [18:0] sram_a; |
wire [3:0] dqp; |
wire [18:0] sram_a; |
wire [3:0] dqp; |
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assign sram_a[18:0] = sram_flash_addr[19:1]; |
wire sram_ce1b, sram_ce2, sram_ce3b; |
wire sram_ce1b, sram_ce2, sram_ce3b; |
assign sram_ce1b = 1'b0; |
assign sram_ce2 = 1'b1; |
assign sram_ce3b = 1'b0; |
446,28 → 458,30
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`ifdef PRELOAD_RAM |
`include "ddr2_model_preload.v" |
`endif |
ddr2_model u_mem0 |
( |
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
.cke (ddr2_cke_sdram[j]), |
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
.ras_n (ddr2_ras_n_sdram), |
.cas_n (ddr2_cas_n_sdram), |
.we_n (ddr2_we_n_sdram), |
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), |
.ba (ddr2_ba_sdram), |
.addr (ddr2_a_sdram), |
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]), |
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]), |
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]), |
.rdqs_n (), |
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
); |
end |
end |
endgenerate |
`endif |
end |
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ddr2_model u_mem0 |
( |
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]), |
.cke (ddr2_cke_sdram[j]), |
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]), |
.ras_n (ddr2_ras_n_sdram), |
.cas_n (ddr2_cas_n_sdram), |
.we_n (ddr2_we_n_sdram), |
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]), |
.ba (ddr2_ba_sdram), |
.addr (ddr2_a_sdram), |
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]), |
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]), |
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]), |
.rdqs_n (), |
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH]) |
); |
end |
end |
endgenerate |
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`endif |
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495,9 → 509,9
`define VCD_SUFFIX ".vcd" |
`endif |
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`ifndef SIM_QUIET |
`ifndef SIM_QUIET |
$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX}); |
`endif |
`endif |
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX}); |
`ifndef VCD_DEPTH |
`define VCD_DEPTH 0 |
523,9 → 537,9
`ifdef END_TIME |
initial begin |
#(`END_TIME); |
`ifndef SIM_QUIET |
`ifndef SIM_QUIET |
$display("* Finish simulation due to END_TIME being set at %t", $time); |
`endif |
`endif |
$finish; |
end |
`endif |