URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
- from Rev 415 to Rev 439
- ↔ Reverse comparison
Rev 415 → Rev 439
/verilog/include/eth_stim.v
76,7 → 76,7
parameter eth_stim_num_rx_only_packet_size = 512; |
parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment |
parameter eth_stim_num_rx_only_packet_size_change_amount = 1; |
parameter eth_stim_num_rx_only_IPG = 800000; // ns |
parameter eth_stim_num_rx_only_IPG = 800000000; // ns |
|
// Do call/response test |
reg eth_stim_do_rx_reponse_to_tx; |
632,7 → 632,9
begin |
//$display("Checking address in tx bd 0x%0h",txpnt_sdram); |
sdram_byte = 8'hx; |
|
`ifdef RAM_WB |
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram); |
`endif |
`ifdef VERSATILE_SDRAM |
sdram0.get_byte(txpnt_sdram,sdram_byte); |
`endif |
1152,9 → 1154,12
begin |
|
sdram_byte = 8'hx; |
`ifdef RAM_WB |
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram); |
`endif |
`ifdef VERSATILE_SDRAM |
sdram0.get_byte(rxpnt_sdram,sdram_byte); |
`endif |
`endif |
`ifdef XILINX_DDR2 |
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte); |
`endif |