URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
- from Rev 485 to Rev 530
- ↔ Reverse comparison
Rev 485 → Rev 530
/verilog/include/eth_stim.v
80,7 → 80,7
|
// Do call/response test |
reg eth_stim_do_rx_reponse_to_tx; |
|
reg eth_stim_do_overflow_test; |
|
parameter num_tx_bds = 16; |
parameter num_tx_bds_mask = 4'hf; |
149,8 → 149,8
expected_rxbd = num_tx_bds; // init this here |
|
eth_stim_do_rx_reponse_to_tx = 0; |
eth_stim_do_overflow_test = 0; |
|
|
while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software |
begin |
#100; |
177,7 → 177,7
eth_phy0.eth_speed, // Speed |
eth_stim_num_rx_only_IPG, // IPG |
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1, |
0, 0); |
0, 0, 0); |
|
eth_stim_waiting = 0; |
end |
199,6 → 199,11
// kickoff call/response here |
eth_stim_do_rx_reponse_to_tx = 1; |
end |
1: |
begin |
// kickoff overflow test here |
eth_stim_do_overflow_test = 1; |
end |
default: |
begin |
do_rx_while_tx_stim(1400); |
227,7 → 232,7
send_packet_loop(num_packets, start_packet_size, 2'b01, 1, |
speed_loop[0], 10000, |
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1, |
inject_errors, inject_errors_mod); |
inject_errors, inject_errors_mod, 0); |
|
end |
|
288,7 → 293,7
$display("do_rx_while_tx packet_size = %0d", packet_size); |
send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0); |
48'h0708_090A_0B0C, 1, 1'b0, 0, 0); |
|
// If RX enable went low, wait for it go high again |
if (ethmac_rxen===1'b0) |
322,6 → 327,15
// Continue if we are enabled |
do_rx_response_to_tx(); |
end |
|
|
// If in call-response mode, whenever we receive a TX packet, we generate |
// one and send it back |
always @(posedge eth_stim_do_overflow_test) |
begin |
// Continue if we are enabled |
do_overflow_stimulus(); |
end |
|
// Generate RX packet in rsponse to TX packet |
task do_rx_response_to_tx; |
358,7 → 372,7
$display("do_rx_response_to_tx packet_size = %0d", packet_size); |
send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0); |
48'h0708_090A_0B0C, 1, 1'b0, 0, 0); |
|
// If RX enable went low, wait for it go high again |
if (ethmac_rxen===1'b0) |
379,10 → 393,117
end |
endtask // do_rx_response_to_tx |
|
// Generate RX packet in rsponse to TX packet |
task do_overflow_stimulus; |
//input unused; |
reg [31:0] IPG; // Inter-packet gap |
reg [31:0] packet_size; |
|
integer j; |
|
begin |
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// Maximum packet size |
packet_size = 1500; |
|
// Minimum IPG |
IPG = eth_stim_IPG_min_100mb; |
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$display("do_overflow_stimulus IPG = %0d", IPG); |
|
|
$display("do_overflow_stimulus packetsize = %0d", packet_size); |
|
send_packet_loop(num_rx_bds, packet_size, 2'b01, 1, |
eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 0); |
|
// This one should cause overflow, don't check it gets there OK |
send_packet_loop(1, packet_size, 2'b01, 1, |
eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 1); |
|
// Wind back expected RXBD number |
if (expected_rxbd == num_tx_bds) |
expected_rxbd = num_tx_bds + num_rx_bds - 1; |
else |
expected_rxbd = expected_rxbd - 1; |
|
// This one should cause overflow, don't check it gets there OK |
send_packet_loop(1, packet_size, 2'b01, 1, |
eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 1); |
|
// Wind back expected RXBD number |
if (expected_rxbd == num_tx_bds) |
expected_rxbd = num_tx_bds + num_rx_bds - 1; |
else |
expected_rxbd = expected_rxbd - 1; |
|
|
// This one should cause overflow, don't check it gets there OK |
send_packet_loop(1, packet_size, 2'b01, 1, |
eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 1); |
|
// Wind back expected RXBD number |
if (expected_rxbd == num_tx_bds) |
expected_rxbd = num_tx_bds + num_rx_bds - 1; |
else |
expected_rxbd = expected_rxbd - 1; |
|
|
// This one should cause overflow, don't check it gets there OK |
send_packet_loop(1, packet_size, 2'b01, 1, |
eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 1); |
|
// Wind back expected RXBD number |
if (expected_rxbd == num_tx_bds) |
expected_rxbd = num_tx_bds + num_rx_bds - 1; |
else |
expected_rxbd = expected_rxbd - 1; |
|
|
// Wait until a buffer descriptor becomes available |
while(`ETH_TOP.wishbone.RxBDRead==1'b1) |
#1000; |
|
$display("%t: RxBDRead gone low",$time); |
#10000; |
|
|
|
send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed, |
IPG, 48'h0012_3456_789a, |
48'h0708_090A_0B0C, 1, 1'b0, 0, 0); |
|
|
// If RX enable went low, wait for it go high again |
if (ethmac_rxen===1'b0) |
begin |
|
while (ethmac_rxen===1'b0) |
begin |
@(posedge ethmac_rxen); |
#10000; |
end |
|
// RX disabled and when re-enabled we reset the buffer |
// descriptor number |
expected_rxbd = num_tx_bds; |
|
end |
|
end |
endtask // do_overflow_stimulus |
|
|
|
// |
// always@() to check the TX buffer descriptors |
// |
653,7 → 774,7
//$display("Checking address in tx bd 0x%0h",txpnt_sdram); |
sdram_byte = 8'hx; |
`ifdef RAM_WB |
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram); |
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(txpnt_sdram); |
`else |
`ifdef VERSATILE_SDRAM |
sdram0.get_byte(txpnt_sdram,sdram_byte); |
707,6 → 828,17
end |
endtask // check_tx_packet |
|
|
// Local buffer of "sent" data to the ethernet MAC, we will check against |
// Size of our local buffer in bytes |
parameter eth_rx_sent_circbuf_size = (16*1024); |
parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1; |
integer eth_rx_sent_circbuf_fill_ptr = 0; |
integer eth_rx_sent_circbuf_read_ptr = 0; |
// The actual buffer |
reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1]; |
|
|
// |
// Task to send a set of packets |
// |
721,8 → 853,9
input [47:0] src_mac; |
input random_fill; |
input random_errors; |
input [31:0] random_error_mod; |
integer j; |
input [31:0] random_error_mod; |
input dont_confirm_rx; |
integer j, k; |
reg error_this_time; |
integer error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO |
reg [31:0] rx_bd_lenstat; |
796,9 → 929,16
// if RX enable still set (might have gone low during this packet |
if (ethmac_rxen) |
begin |
if (error_this_time) |
if (error_this_time || dont_confirm_rx) begin |
// Put in dummy length, checking function will skip... |
rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee; |
|
for(k=0;k<length;k=k+1) |
// skip data in verify buffer |
eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)& |
eth_rx_sent_circbuf_size_mask; |
|
end |
else |
rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length; |
|
849,15 → 989,6
end // for (j=0;j<num_packets | length <32;j=j+1) |
end |
endtask // send_packet_loop |
|
// Local buffer of "sent" data to the ethernet MAC, we will check against |
// Size of our local buffer in bytes |
parameter eth_rx_sent_circbuf_size = (16*1024); |
parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1; |
integer eth_rx_sent_circbuf_fill_ptr = 0; |
integer eth_rx_sent_circbuf_read_ptr = 0; |
// The actual buffer |
reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1]; |
|
/* |
TASKS for set and check RX packets: |
1176,13 → 1307,18
begin |
|
sdram_byte = 8'hx; |
`ifdef XILINX_DDR2 |
|
`ifdef RAM_WB |
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(rxpnt_sdram); |
`else |
`ifdef XILINX_DDR2 |
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte); |
`else |
`else |
$display(" * Error:"); |
|
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx"); |
$finish; |
`endif |
`endif |
|
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr]; |