URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2
- from Rev 412 to Rev 439
- ↔ Reverse comparison
Rev 412 → Rev 439
/xilinx_ddr2.v
181,6 → 181,8
.wb_ack_o (wbs_ram_ack_o), |
.wb_adr_i (wbs_ram_adr_i[31:0]), |
.wb_stb_i (wbs_ram_stb_i), |
.wb_cti_i (wbs_ram_cti_i), |
.wb_bte_i (wbs_ram_bte_i), |
.wb_cyc_i (wbs_ram_cyc_i), |
.wb_we_i (wbs_ram_we_i), |
.wb_sel_i (wbs_ram_sel_i[3:0]), |
/xilinx_ddr2_if.v
104,6 → 104,8
input [31:0] wb_adr_i, |
input wb_stb_i, |
input wb_cyc_i, |
input [2:0] wb_cti_i, |
input [1:0] wb_bte_i, |
input wb_we_i, |
input [3:0] wb_sel_i, |
input [31:0] wb_dat_i, |
199,7 → 201,6
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out; |
wire phy_init_done; |
|
|
assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid; |
|
// Wishbone request detection |
366,7 → 367,8
always @(posedge ddr2_clk) |
if (ddr2_rst) |
ddr2_read_done <= 0; |
else if (!rd_data_valid & rd_data_valid_r) // Detect read data valid falling edge |
// Detect read data valid falling edge |
else if (!rd_data_valid & rd_data_valid_r) |
ddr2_read_done <= 1; |
else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain |
ddr2_read_done <= 0; |