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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog
- from Rev 412 to Rev 415
- ↔ Reverse comparison
Rev 412 → Rev 415
/include/or1200_defines.v
1725,8 → 1725,8
// used to determine where vectors are located. // |
/////////////////////////////////////////////////////////////////////////////// |
// Boot from 0xf0000100 |
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f |
//`define OR1200_BOOT_ADR 32'hf0000100 |
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f |
`define OR1200_BOOT_ADR 32'hf0000100 |
// Boot from 0x100 |
`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f |
`define OR1200_BOOT_ADR 32'h00000100 |
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f |
// `define OR1200_BOOT_ADR 32'h00000100 |
/include/orpsoc-defines.v
72,7 → 72,9
//`define ARBITER_IBUS_REGISTERING |
`define ARBITER_IBUS_WATCHDOG |
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles |
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12 |
// This has to be kind of long, as DDR2 initialisation can take a little while |
// and after reset, and if this is too short we'll always get bus error. |
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20 |
|
// Data bus arbiter |
|
79,7 → 81,7
//`define ARBITER_DBUS_REGISTERING |
`define ARBITER_DBUS_WATCHDOG |
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles |
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12 |
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20 |
|
// Byte bus (peripheral bus) arbiter |
// Don't really need the watchdog here - the databus will pick it up |
/orpsoc_top/orpsoc_top.v
55,7 → 55,7
uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o, |
`endif |
`ifdef SPI0 |
spi0_sck_o, spi0_mosi_o, spi0_miso_i, spi0_ss_o, |
spi0_mosi_o, spi0_ss_o,/* spi0_sck_o, spi0_miso_i,via STARTUP_VIRTEX5*/ |
`endif |
`ifdef I2C0 |
i2c0_sda_io, i2c0_scl_io, |
133,10 → 133,12
output uart0_stx_expheader_pad_o; |
`endif |
`ifdef SPI0 |
output spi0_sck_o; |
output spi0_mosi_o; |
output [spi0_ss_width-1:0] spi0_ss_o; |
output [spi0_ss_width-1:0] spi0_ss_o; |
/* via STARTUP_VIRTEX5 |
output spi0_sck_o; |
input spi0_miso_i; |
*/ |
`endif |
`ifdef I2C0 |
inout i2c0_sda_io, i2c0_scl_io; |
1227,7 → 1229,7
assign wbs_d_uart0_rty_o = 0; |
|
// Two UART lines coming to single one (ensure they go high when unconnected) |
assign uart_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i; |
assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i; |
assign uart0_stx_pad_o = uart0_stx; |
assign uart0_stx_expheader_pad_o = uart0_stx; |
|
1315,6 → 1317,23
); |
|
defparam spi0.slave_select_width = spi0_ss_width; |
|
// SPI clock and MISO lines must go through STARTUP_VIRTEX5 block. |
STARTUP_VIRTEX5 startup_virtex5 |
( |
.CFGCLK(), |
.CFGMCLK(), |
.DINSPI(spi0_miso_i), |
.EOS(), |
.TCKSPI(), |
.CLK(), |
.GSR(1'b0), |
.GTS(1'b0), |
.USRCCLKO(spi0_sck_o), |
.USRCCLKTS(1'b0), |
.USRDONEO(), |
.USRDONETS() |
); |
|
//////////////////////////////////////////////////////////////////////// |
`else // !`ifdef SPI0 |