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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
- from Rev 426 to Rev 435
- ↔ Reverse comparison
Rev 426 → Rev 435
/verilog/include/or1200_defines.v
349,6 → 349,7
// |
`define OR1200_IMPL_ALU_FFL1 |
|
|
// |
// Implement multiplier |
// |
360,7 → 361,7
// Implement multiply-and-accumulate |
// |
// By default MAC is implemented. To |
// implement MAC, multiplier needs to be |
// implement MAC, multiplier (non-serial) needs to be |
// implemented. |
// |
`define OR1200_MAC_IMPLEMENTED |
369,23 → 370,22
// Implement optional l.div/l.divu instructions |
// |
// By default divide instructions are not implemented |
// to save area and increase clock frequency. or32 C/C++ |
// compiler can use soft library for division. |
// to save area. |
// |
// To implement divide, both multiplier and MAC needs to be implemented. |
// |
`define OR1200_DIV_IMPLEMENTED |
|
// |
// Low power, slower multiplier |
// Serial multiplier. |
// |
// Select between low-power (larger) multiplier |
// and faster multiplier. The actual difference |
// is only AND logic that prevents distribution |
// of operands into the multiplier when instruction |
// in execution is not multiply instruction |
//`define OR1200_MULT_SERIAL |
|
// |
//`define OR1200_LOWPWR_MULT |
// Serial divider. |
// Uncomment to use a serial divider, otherwise will |
// be a generic parallel implementation. |
// |
`define OR1200_DIV_SERIAL |
|
// |
// Implement HW Single Precision FPU |
464,7 → 464,8
`define OR1200_ALUOP_SHROT 4'd8 |
`define OR1200_ALUOP_DIV 4'd9 |
`define OR1200_ALUOP_DIVU 4'd10 |
/* Order not specifically defined. */ |
`define OR1200_ALUOP_MULU 4'd11 |
/* Values sent to ALU from decode unit - not strictly defined by ISA */ |
`define OR1200_ALUOP_IMM 4'd11 |
`define OR1200_ALUOP_MOVHI 4'd12 |
`define OR1200_ALUOP_COMP 4'd13 |