URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
- from Rev 435 to Rev 439
- ↔ Reverse comparison
Rev 435 → Rev 439
/verilog/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this |
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`ifdef ETH_TX_FULL_PACKET_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 11 |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_DEPTH 375 |
`else |
`ifdef ETH_TX_1KBYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_CNT_WIDTH 8 |
`define ETH_TX_FIFO_DEPTH 256 |
`else |
`ifdef ETH_TX_512BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 8 |
`define ETH_TX_FIFO_CNT_WIDTH 7 |
`define ETH_TX_FIFO_DEPTH 128 |
`else |
`ifdef ETH_TX_256BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 7 |
`define ETH_TX_FIFO_CNT_WIDTH 6 |
`define ETH_TX_FIFO_DEPTH 64 |
`else |
// Default is 64 bytes |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_CNT_WIDTH 4 |
`define ETH_TX_FIFO_DEPTH 16 |
`endif |
`endif |
217,15 → 217,15
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// Settings for RX FIFO |
`define ETH_RX_FIFO_CNT_WIDTH 9 |
`define ETH_RX_FIFO_CNT_WIDTH 8 |
`define ETH_RX_FIFO_DEPTH 256 |
//`define ETH_RX_FIFO_CNT_WIDTH 8 |
//`define ETH_RX_FIFO_CNT_WIDTH 7 |
//`define ETH_RX_FIFO_DEPTH 128 |
//`define ETH_RX_FIFO_CNT_WIDTH 7 |
//`define ETH_RX_FIFO_CNT_WIDTH 6 |
//`define ETH_RX_FIFO_DEPTH 64 |
//`define ETH_RX_FIFO_CNT_WIDTH 6 |
//`define ETH_RX_FIFO_CNT_WIDTH 5 |
//`define ETH_RX_FIFO_DEPTH 32 |
//`define ETH_RX_FIFO_CNT_WIDTH 5 |
//`define ETH_RX_FIFO_CNT_WIDTH 4 |
//`define ETH_RX_FIFO_DEPTH 16 |
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`define ETH_RX_FIFO_DATA_WIDTH 32 |
/verilog/xilinx_ddr2/xilinx_ddr2.v
181,6 → 181,8
.wb_ack_o (wbs_ram_ack_o), |
.wb_adr_i (wbs_ram_adr_i[31:0]), |
.wb_stb_i (wbs_ram_stb_i), |
.wb_cti_i (wbs_ram_cti_i), |
.wb_bte_i (wbs_ram_bte_i), |
.wb_cyc_i (wbs_ram_cyc_i), |
.wb_we_i (wbs_ram_we_i), |
.wb_sel_i (wbs_ram_sel_i[3:0]), |
/verilog/xilinx_ddr2/xilinx_ddr2_if.v
104,6 → 104,8
input [31:0] wb_adr_i, |
input wb_stb_i, |
input wb_cyc_i, |
input [2:0] wb_cti_i, |
input [1:0] wb_bte_i, |
input wb_we_i, |
input [3:0] wb_sel_i, |
input [31:0] wb_dat_i, |
199,7 → 201,6
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out; |
wire phy_init_done; |
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assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid; |
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// Wishbone request detection |
366,7 → 367,8
always @(posedge ddr2_clk) |
if (ddr2_rst) |
ddr2_read_done <= 0; |
else if (!rd_data_valid & rd_data_valid_r) // Detect read data valid falling edge |
// Detect read data valid falling edge |
else if (!rd_data_valid & rd_data_valid_r) |
ddr2_read_done <= 1; |
else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain |
ddr2_read_done <= 0; |
/verilog/orpsoc_top/orpsoc_top.v
1037,8 → 1037,8
.wbm0_stb_i (wbs_i_mc0_stb_i), |
.wbm0_dat_o (wbs_i_mc0_dat_o), |
.wbm0_ack_o (wbs_i_mc0_ack_o), |
.wbm0_err_o (), |
.wbm0_rty_o (), |
.wbm0_err_o (wbs_i_mc0_err_o), |
.wbm0_rty_o (wbs_i_mc0_rty_o), |
// Wishbone slave interface 1 |
.wbm1_dat_i (wbs_d_mc0_dat_i), |
.wbm1_adr_i (wbs_d_mc0_adr_i), |
1050,22 → 1050,30
.wbm1_stb_i (wbs_d_mc0_stb_i), |
.wbm1_dat_o (wbs_d_mc0_dat_o), |
.wbm1_ack_o (wbs_d_mc0_ack_o), |
.wbm1_err_o (), |
.wbm1_rty_o (), |
.wbm1_err_o (wbs_d_mc0_err_o), |
.wbm1_rty_o (wbs_d_mc0_rty_o), |
// Wishbone slave interface 2 |
.wbm2_dat_i (wbm_eth0_dat_o), |
.wbm2_adr_i (wbm_eth0_adr_o), |
.wbm2_sel_i (wbm_eth0_sel_o), |
.wbm2_cti_i (wbm_eth0_cti_o), |
.wbm2_bte_i (wbm_eth0_bte_o), |
.wbm2_we_i (wbm_eth0_we_o ), |
.wbm2_cyc_i (wbm_eth0_cyc_o), |
.wbm2_stb_i (wbm_eth0_stb_o), |
.wbm2_dat_o (wbm_eth0_dat_i), |
.wbm2_ack_o (wbm_eth0_ack_i), |
.wbm2_err_o (wbm_eth0_err_i), |
.wbm2_rty_o (wbm_eth0_rty_i), |
// Clock, reset |
.wb_clk_i (wb_clk), |
.wb_rst_i (wb_rst)); |
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assign wbs_i_mc0_err_o = 0; |
assign wbs_i_mc0_rty_o = 0; |
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assign wbs_d_mc0_err_o = 0; |
assign wbs_d_mc0_rty_o = 0; |
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defparam ram_wb0.aw = wb_aw; |
defparam ram_wb0.dw = wb_dw; |
defparam ram_wb0.mem_span = internal_sram_mem_span; |
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span; |
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defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB |
defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024) |
//////////////////////////////////////////////////////////////////////// |
`endif // `ifdef RAM_WB |
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