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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
    from Rev 485 to Rev 496
    Reverse comparison

Rev 485 → Rev 496

/verilog/clkgen/clkgen.v
144,8 → 144,8
defparam dcm0.CLKFX_MULTIPLY = 4;
defparam dcm0.CLKFX_DIVIDE = 3;
 
// Generate 50 MHz from CLKDV
defparam dcm0.CLKDV_DIVIDE = 4.0;
// Generate 66 MHz from CLKDV
defparam dcm0.CLKDV_DIVIDE = 3.0;
 
BUFG dcm0_clk0_bufg
(// Outputs
/verilog/include/uart_defines.v
246,5 → 246,9
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd11
// 50MHz: prescaler 27.1
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd27
// 66MHz: prescaler 36.1
`define PRESCALER_HIGH_PRESET 8'd0
`define PRESCALER_LOW_PRESET 8'd27
`define PRESCALER_LOW_PRESET 8'd36
 

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