URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
- from Rev 499 to Rev 502
- ↔ Reverse comparison
Rev 499 → Rev 502
/verilog/include/ethmac_defines.v
225,12 → 225,12
//`define ETH_RX_FIFO_DEPTH 256 |
//`define ETH_RX_FIFO_CNT_WIDTH 7 |
//`define ETH_RX_FIFO_DEPTH 128 |
//`define ETH_RX_FIFO_CNT_WIDTH 6 |
//`define ETH_RX_FIFO_DEPTH 64 |
`define ETH_RX_FIFO_CNT_WIDTH 6 |
`define ETH_RX_FIFO_DEPTH 64 |
//`define ETH_RX_FIFO_CNT_WIDTH 5 |
//`define ETH_RX_FIFO_DEPTH 32 |
`define ETH_RX_FIFO_CNT_WIDTH 4 |
`define ETH_RX_FIFO_DEPTH 16 |
//`define ETH_RX_FIFO_CNT_WIDTH 4 |
//`define ETH_RX_FIFO_DEPTH 16 |
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`define ETH_RX_FIFO_DATA_WIDTH 32 |
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/verilog/include/or1200_defines.v
299,7 → 299,7
// If you don't use them, then disable implementation |
// to save area. |
// |
//`define OR1200_IMPL_ADDC |
`define OR1200_IMPL_ADDC |
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// |
// Implement l.sub instruction |
321,9 → 321,26
// instructions and if these three insns are not |
// implemented there is not much point having SR[CY]. |
// |
//`define OR1200_IMPL_CY |
`define OR1200_IMPL_CY |
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// |
// Implement carry bit SR[OV] |
// |
// Compiler doesn't use this, but other code may like |
// to. |
// |
`define OR1200_IMPL_OV |
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// |
// Implement carry bit SR[OVE] |
// |
// Overflow interrupt indicator. When enabled, SR[OV] flag |
// does not remain asserted after exception. |
// |
`define OR1200_IMPL_OVE |
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// |
// Implement rotate in the ALU |
// |
// At the time of writing this, or32 |
825,9 → 842,9
`define OR1200_SR_LEE 7 |
`define OR1200_SR_CE 8 |
`define OR1200_SR_F 9 |
`define OR1200_SR_CY 10 // Unused |
`define OR1200_SR_OV 11 // Unused |
`define OR1200_SR_OVE 12 // Unused |
`define OR1200_SR_CY 10 // Optional |
`define OR1200_SR_OV 11 // Optional |
`define OR1200_SR_OVE 12 // Optional |
`define OR1200_SR_DSX 13 // Unused |
`define OR1200_SR_EPH 14 |
`define OR1200_SR_FO 15 |
/verilog/include/uart_defines.v
240,7 → 240,7
`define FAST_TEST 1 // 64/1024 packets are sent |
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// Defines hard baud prescaler register - uncomment to enable |
`define PRESCALER_PRESET_HARD |
//`define PRESCALER_PRESET_HARD |
// 115200 baud preset values |
// 20MHz: prescaler 10.8 (11, rounded up) |
//`define PRESCALER_HIGH_PRESET 8'd0 |
249,6 → 249,6
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd27 |
// 66MHz: prescaler 36.1 |
`define PRESCALER_HIGH_PRESET 8'd0 |
`define PRESCALER_LOW_PRESET 8'd36 |
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd36 |
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