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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
    from Rev 503 to Rev 530
    ↔ Reverse comparison
  •

Rev 503 → Rev 530

/verilog/include/ethmac_defines.v
46,24 → 46,11
 
// Generic FIFO implementation - hopefully synthesizable with Synplify
//`define ETH_FIFO_GENERIC
// Ethernet implemented in Xilinx Chips (uncomment following lines)
`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
// Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
// specific elements.
`define ETH_FIFO_XILINX
//`define ETH_FIFO_RAMB18
 
// Ethernet implemented in Altera Chips (uncomment following lines)
//`define ETH_ALTERA_ALTSYNCRAM
 
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
 
// Ethernet implemented in ASIC with Artisan RAMs
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
 
// Uncomment when Avalon bus is used
//`define ETH_AVALON_BUS
 
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
185,48 → 172,49
`define ETH_TX_FIFO_DATA_WIDTH 32
 
// Defines for ethernet TX fifo size - impacts FPGA resource usage
//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
 
//`define ETH_TX_64BYTE_FIFO // 64 byte TX buffer - uncomment this
//`define ETH_TX_128BYTE_FIFO // 128 byte TX buffer - uncomment this
`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
//`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
`ifdef ETH_TX_128BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_DEPTH 32
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
`endif
`endif // !`ifdef ETH_TX_512BYTE_FIFO
`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
`endif
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`endif
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`endif
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`endif
`ifdef ETH_TX_128BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_DEPTH 32
`endif
`ifdef ETH_TX_128BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
 
 
 
 
// Settings for RX FIFO
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
`define ETH_RX_FIFO_DEPTH 128
`define ETH_RX_FIFO_CNT_WIDTH 6
`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 4
/verilog/include/orpsoc-defines.v
74,7 → 74,11
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
// This has to be kind of long, as DDR2 initialisation can take a little while
// and after reset, and if this is too short we'll always get bus error.
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`ifdef XILINX_DDR2
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Data bus arbiter
 
81,7 → 85,11
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`ifdef XILINX_DDR2
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
/verilog/orpsoc_top/orpsoc_top.v
114,16 → 114,16
`endif
`ifdef XILINX_SSRAM
// ZBT SSRAM
output sram_clk,
input sram_clk_fb,
output [21:1] sram_flash_addr,
inout [31:0] sram_flash_data,
output sram_cen,
output sram_flash_oe_n,
output sram_flash_we_n,
output [3:0] sram_bw,
output sram_adv_ld_n,
output sram_mode,
output sram_clk;
input sram_clk_fb;
output [21:1] sram_flash_addr;
inout [31:0] sram_flash_data;
output sram_cen;
output sram_flash_oe_n;
output sram_flash_we_n;
output [3:0] sram_bw;
output sram_adv_ld_n;
output sram_mode;
`endif
`ifdef UART0
input uart0_srx_pad_i;

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