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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
    from Rev 530 to Rev 655
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  •

Rev 530 → Rev 655

/verilog/include/or1200_defines.v
862,7 → 862,7
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
`define OR1200_SR_EPH_DEF 1'b1
 
 
//
1814,9 → 1814,12
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xe0000100
`define OR1200_BOOT_PCREG_DEFAULT 30'h3800003f
`define OR1200_BOOT_ADR 32'he0000100
// Boot from 0xf0000100
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
`define OR1200_BOOT_ADR 32'hf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
//`define OR1200_BOOT_ADR 32'h00000100
/verilog/include/orpsoc-defines.v
51,10 → 51,11
`define JTAG_DEBUG
// `define RAM_WB
// `define XILINX_SSRAM
`define CFI_FLASH
`define XILINX_DDR2
`define UART0
`define GPIO0
`define SPI0
// `define SPI0
`define I2C0
`define I2C1
`define ETH0
/verilog/include/orpsoc-params.v
80,8 → 80,15
// ROM
parameter wbs_i_rom0_data_width = 32;
parameter wbs_i_rom0_addr_width = 6;
parameter rom0_wb_adr = 4'hf;
parameter rom0_wb_adr = 4'he;
 
// CFI flash
parameter wbs_i_flash_data_width = 32;
parameter wbs_i_flash_addr_width = 32;
parameter wbs_d_flash_data_width = 32;
parameter wbs_d_flash_addr_width = 32;
parameter flash_wb_adr = 4'hf;
 
// MC0 (SDRAM, or other)
parameter wbs_i_mc0_data_width = 32;
parameter wbs_d_mc0_data_width = 32;
94,9 → 101,14
parameter wbm_eth0_addr_width = 32;
 
// Memory sizing for synthesis (small)
parameter internal_sram_mem_span = 32'h0080_0000;
parameter internal_sram_adr_width_for_span = 23;
//parameter internal_sram_mem_span = 32'h0200_0000; /* 32MB */
//parameter internal_sram_adr_width_for_span = 25;
//parameter internal_sram_mem_span = 32'h0080_0000; /* 8MB */
//parameter internal_sram_adr_width_for_span = 23;
parameter internal_sram_mem_span = 32'h0001_0000; /* 64KB */
parameter internal_sram_adr_width_for_span = 17;
 
 
//////////////////////////////////////////////////////
// //
// Wishbone bus parameters //
119,8 → 131,9
///////////////////////////
parameter ibus_arb_addr_match_width = 4;
// Slave addresses
parameter ibus_arb_slave0_adr = rom0_wb_adr; // FLASH ROM
parameter ibus_arb_slave0_adr = rom0_wb_adr; // ROM
parameter ibus_arb_slave1_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
parameter ibus_arb_slave2_adr = flash_wb_adr; // Flash
 
///////////////////////////
// //
133,6 → 146,7
// Slave addresses
parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0
parameter dbus_arb_slave2_adr = flash_wb_adr; // Flash
 
///////////////////////////////
// //
/verilog/orpsoc_top/orpsoc_top.v
49,6 → 49,11
sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data,
sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw,
sram_adv_ld_n, sram_mode,
`endif
`ifdef CFI_FLASH
flash_dq_io, flash_adr_o, flash_adv_n_o, flash_ce_n_o,
flash_clk_o, flash_oe_n_o, flash_rst_n_o, flash_wait_i,
flash_we_n_o,
`endif
`ifdef UART0
uart0_srx_pad_i, uart0_stx_pad_o,
124,7 → 129,18
output [3:0] sram_bw;
output sram_adv_ld_n;
output sram_mode;
`endif
`endif // `ifdef XILINX_SSRAM
`ifdef CFI_FLASH
inout [15:0] flash_dq_io;
output [23:0] flash_adr_o;
output flash_adv_n_o;
output flash_ce_n_o;
output flash_clk_o;
output flash_oe_n_o;
output flash_rst_n_o;
input flash_wait_i;
output flash_we_n_o;
`endif
`ifdef UART0
input uart0_srx_pad_i;
output uart0_stx_pad_o;
308,6 → 324,20
wire wbs_i_mc0_ack_o;
wire wbs_i_mc0_err_o;
wire wbs_i_mc0_rty_o;
 
// flash instruction bus wires
wire [31:0] wbs_i_flash_adr_i;
wire [wbs_i_flash_data_width-1:0] wbs_i_flash_dat_i;
wire [3:0] wbs_i_flash_sel_i;
wire wbs_i_flash_we_i;
wire wbs_i_flash_cyc_i;
wire wbs_i_flash_stb_i;
wire [2:0] wbs_i_flash_cti_i;
wire [1:0] wbs_i_flash_bte_i;
wire [wbs_i_flash_data_width-1:0] wbs_i_flash_dat_o;
wire wbs_i_flash_ack_o;
wire wbs_i_flash_err_o;
wire wbs_i_flash_rty_o;
// Data bus slave wires //
423,6 → 453,20
wire wbm_eth0_err_i;
wire wbm_eth0_rty_i;
 
// flash slave wires
wire [31:0] wbs_d_flash_adr_i;
wire [wbs_d_flash_data_width-1:0] wbs_d_flash_dat_i;
wire [3:0] wbs_d_flash_sel_i;
wire wbs_d_flash_we_i;
wire wbs_d_flash_cyc_i;
wire wbs_d_flash_stb_i;
wire [2:0] wbs_d_flash_cti_i;
wire [1:0] wbs_d_flash_bte_i;
wire [wbs_d_flash_data_width-1:0] wbs_d_flash_dat_o;
wire wbs_d_flash_ack_o;
wire wbs_d_flash_err_o;
wire wbs_d_flash_rty_o;
 
 
//
479,6 → 523,22
.wbs1_err_o (wbs_i_mc0_err_o),
.wbs1_rty_o (wbs_i_mc0_rty_o),
 
// Slave 2
// Inputs to slave from arbiter
.wbs2_adr_i (wbs_i_flash_adr_i),
.wbs2_dat_i (wbs_i_flash_dat_i),
.wbs2_sel_i (wbs_i_flash_sel_i),
.wbs2_we_i (wbs_i_flash_we_i),
.wbs2_cyc_i (wbs_i_flash_cyc_i),
.wbs2_stb_i (wbs_i_flash_stb_i),
.wbs2_cti_i (wbs_i_flash_cti_i),
.wbs2_bte_i (wbs_i_flash_bte_i),
// Outputs from slave to arbiter
.wbs2_dat_o (wbs_i_flash_dat_o),
.wbs2_ack_o (wbs_i_flash_ack_o),
.wbs2_err_o (wbs_i_flash_err_o),
.wbs2_rty_o (wbs_i_flash_rty_o),
 
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
485,8 → 545,9
 
defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width;
 
defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM
defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory
defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // flash ROM
defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // main memory
defparam arbiter_ibus0.slave2_adr = ibus_arb_slave2_adr; // CFI flash
 
//
// Wishbone data bus arbiter
553,19 → 614,32
.wbs1_ack_o (wbs_d_eth0_ack_o),
.wbs1_err_o (wbs_d_eth0_err_o),
.wbs1_rty_o (wbs_d_eth0_rty_o),
 
.wbs2_adr_i (wbs_d_flash_adr_i),
.wbs2_dat_i (wbs_d_flash_dat_i),
.wbs2_sel_i (wbs_d_flash_sel_i),
.wbs2_we_i (wbs_d_flash_we_i),
.wbs2_cyc_i (wbs_d_flash_cyc_i),
.wbs2_stb_i (wbs_d_flash_stb_i),
.wbs2_cti_i (wbs_d_flash_cti_i),
.wbs2_bte_i (wbs_d_flash_bte_i),
.wbs2_dat_o (wbs_d_flash_dat_o),
.wbs2_ack_o (wbs_d_flash_ack_o),
.wbs2_err_o (wbs_d_flash_err_o),
.wbs2_rty_o (wbs_d_flash_rty_o),
.wbs2_adr_i (wbm_b_d_adr_o),
.wbs2_dat_i (wbm_b_d_dat_o),
.wbs2_sel_i (wbm_b_d_sel_o),
.wbs2_we_i (wbm_b_d_we_o),
.wbs2_cyc_i (wbm_b_d_cyc_o),
.wbs2_stb_i (wbm_b_d_stb_o),
.wbs2_cti_i (wbm_b_d_cti_o),
.wbs2_bte_i (wbm_b_d_bte_o),
.wbs2_dat_o (wbm_b_d_dat_i),
.wbs2_ack_o (wbm_b_d_ack_i),
.wbs2_err_o (wbm_b_d_err_i),
.wbs2_rty_o (wbm_b_d_rty_i),
.wbs3_adr_i (wbm_b_d_adr_o),
.wbs3_dat_i (wbm_b_d_dat_o),
.wbs3_sel_i (wbm_b_d_sel_o),
.wbs3_we_i (wbm_b_d_we_o),
.wbs3_cyc_i (wbm_b_d_cyc_o),
.wbs3_stb_i (wbm_b_d_stb_o),
.wbs3_cti_i (wbm_b_d_cti_o),
.wbs3_bte_i (wbm_b_d_bte_o),
.wbs3_dat_o (wbm_b_d_dat_i),
.wbs3_ack_o (wbm_b_d_ack_i),
.wbs3_err_o (wbm_b_d_err_i),
.wbs3_rty_o (wbm_b_d_rty_i),
 
// Clock, reset inputs
.wb_clk (wb_clk),
576,6 → 650,7
defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;
defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
defparam arbiter_dbus0.slave2_adr = dbus_arb_slave2_adr;
 
//
// Wishbone byte-wide bus arbiter
1072,12 → 1147,128
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB
defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024)
defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
 
`ifdef CFI_FLASH
 
/* Lighweight arbiter between instruction and data busses going
into the CFI controller */
 
wire [31:0] flash_wb_adr_i;
wire [31:0] flash_wb_dat_i;
wire [31:0] flash_wb_dat_o;
wire [3:0] flash_wb_sel_i;
wire flash_wb_cyc_i;
wire flash_wb_stb_i;
wire flash_wb_we_i;
wire flash_wb_ack_o;
 
reg [1:0] flash_mst_sel;
reg [9:0] flash_arb_timeout;
wire flash_arb_reset;
always @(posedge wb_clk)
if (wb_rst)
flash_mst_sel <= 0;
else begin
if (flash_mst_sel==2'b00) begin
/* wait for new access from masters. data takes priority */
if (wbs_d_flash_cyc_i & wbs_d_flash_stb_i)
flash_mst_sel[1] <= 1;
else if (wbs_i_flash_cyc_i & wbs_i_flash_stb_i)
flash_mst_sel[0] <= 1;
end
else begin
if (flash_wb_ack_o | flash_arb_reset)
flash_mst_sel <= 0;
end // else: !if(flash_mst_sel==2'b00)
end // else: !if(wb_rst)
assign flash_wb_adr_i = flash_mst_sel[0] ? wbs_i_flash_adr_i :
wbs_d_flash_adr_i;
assign flash_wb_dat_i = flash_mst_sel[0] ? wbs_i_flash_dat_i :
wbs_d_flash_dat_i;
assign flash_wb_stb_i = flash_mst_sel[0] ? wbs_i_flash_stb_i :
flash_mst_sel[1] ? wbs_d_flash_stb_i : 0;
assign flash_wb_cyc_i = flash_mst_sel[0] ? wbs_i_flash_cyc_i :
flash_mst_sel[1] ? wbs_d_flash_cyc_i : 0;
assign flash_wb_we_i = flash_mst_sel[0] ? wbs_i_flash_we_i :
wbs_d_flash_we_i;
assign flash_wb_sel_i = flash_mst_sel[0] ? wbs_i_flash_sel_i :
wbs_d_flash_sel_i;
 
assign wbs_i_flash_dat_o = flash_wb_dat_o;
assign wbs_d_flash_dat_o = flash_wb_dat_o;
assign wbs_i_flash_ack_o = flash_wb_ack_o & flash_mst_sel[0];
assign wbs_d_flash_ack_o = flash_wb_ack_o & flash_mst_sel[1];
assign wbs_i_flash_err_o = flash_arb_reset & flash_mst_sel[0];
assign wbs_i_flash_rty_o = 0;
assign wbs_d_flash_err_o = flash_arb_reset & flash_mst_sel[1];
assign wbs_d_flash_rty_o = 0;
 
always @(posedge wb_clk)
if (wb_rst)
flash_arb_timeout <= 0;
else if (flash_wb_ack_o)
flash_arb_timeout <= 0;
else if (flash_wb_stb_i & flash_wb_cyc_i)
flash_arb_timeout <= flash_arb_timeout + 1;
 
assign flash_arb_reset = (&flash_arb_timeout);
cfi_ctrl
/* Use the simple flash interface */
#(.cfi_engine("DISABLED"))
cfi_ctrl0
(
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst | flash_arb_reset),
 
.wb_adr_i(flash_wb_adr_i),
.wb_dat_i(flash_wb_dat_i),
.wb_stb_i(flash_wb_stb_i),
.wb_cyc_i(flash_wb_cyc_i),
.wb_we_i (flash_wb_we_i ),
.wb_sel_i(flash_wb_sel_i),
.wb_dat_o(flash_wb_dat_o),
.wb_ack_o(flash_wb_ack_o),
.wb_err_o(),
.wb_rty_o(),
.flash_dq_io(flash_dq_io),
.flash_adr_o(flash_adr_o),
.flash_adv_n_o(flash_adv_n_o),
.flash_ce_n_o(flash_ce_n_o),
.flash_clk_o(flash_clk_o),
.flash_oe_n_o(flash_oe_n_o),
.flash_rst_n_o(flash_rst_n_o),
.flash_wait_i(flash_wait_i),
.flash_we_n_o(flash_we_n_o),
.flash_wp_n_o()
);
 
`else
 
assign wbs_i_flash_dat_o = 0;
assign wbs_i_flash_ack_o = 0;
assign wbs_i_flash_err_o = 0;
assign wbs_i_flash_rty_o = 0;
 
assign wbs_d_flash_dat_o = 0;
assign wbs_d_flash_ack_o = 0;
assign wbs_d_flash_err_o = 0;
assign wbs_d_flash_rty_o = 0;
`endif // `ifdef CFI_FLASH
`ifdef ETH0
 
//
/verilog/arbiter/arbiter_dbus.v
117,7 → 117,7
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
/*
 
// Slave four
// Wishbone Slave interface
wbs3_adr_i,
133,7 → 133,7
wbs3_ack_o,
wbs3_err_o,
wbs3_rty_o,
 
/*
// Slave five
// Wishbone Slave interface
wbs4_adr_i,
450,7 → 450,7
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
/*
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs3_adr_i;
465,7 → 465,7
input wbs3_ack_o;
input wbs3_err_o;
input wbs3_rty_o;
 
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs4_adr_i;
870,14 → 870,15
//
// Slave selects
//
assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here
assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr;
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
assign wb_slave_sel[2] = wbm_adr_o[31:28] == slave2_adr;
// Auto select last slave when others are not selected
assign wb_slave_sel[2] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]);
assign wb_slave_sel[3] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]
| wb_slave_sel_r[2]);
 
/*
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
/*
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
941,7 → 942,6
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0];
 
 
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
956,7 → 956,6
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1];
 
 
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
970,7 → 969,6
assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2];
assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2];
assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2];
/*
 
// Slave 3 inputs
assign wbs3_adr_i = wbm_adr_o;
985,7 → 983,7
assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3];
assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3];
assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3];
 
/*
// Slave 4 inputs
assign wbs4_adr_i = wbm_adr_o;
assign wbs4_dat_i = wbm_dat_o;
1188,8 → 1186,8
assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] :
wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] :
/* wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
/* wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] :
wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] :
wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] :
1208,8 → 1206,8
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] |
wbs_ack_o_mux_i[2] /*|
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[2] |
wbs_ack_o_mux_i[3] /*|
wbs_ack_o_mux_i[4] |
wbs_ack_o_mux_i[5] |
wbs_ack_o_mux_i[6] |
1228,8 → 1226,8
 
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |
wbs_err_o_mux_i[2] |/*
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[2] |
wbs_err_o_mux_i[3] |/*
wbs_err_o_mux_i[4] |
wbs_err_o_mux_i[5] |
wbs_err_o_mux_i[6] |
1248,8 → 1246,8
 
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1] |
wbs_rty_o_mux_i[2] /*|
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[2] |
wbs_rty_o_mux_i[3] /*|
wbs_rty_o_mux_i[4] |
wbs_rty_o_mux_i[5] |
wbs_rty_o_mux_i[6] |
/verilog/arbiter/arbiter_ibus.v
10,7 → 10,7
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// Copyright (C) 2009, 2010, 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
87,6 → 87,24
wbs1_err_o,
wbs1_rty_o,
 
 
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
wbs2_dat_i,
wbs2_sel_i,
wbs2_we_i,
wbs2_cyc_i,
wbs2_stb_i,
wbs2_cti_i,
wbs2_bte_i,
wbs2_dat_o,
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
wb_clk,
wb_rst
);
97,8 → 115,9
 
parameter wb_addr_match_width = 8;
 
parameter slave0_adr = 8'hf0; // FLASH ROM
parameter slave0_adr = 8'he0; // FLASH ROM
parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM)
parameter slave2_adr = 8'hf0; // External flash
 
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
148,8 → 167,24
input wbs1_err_o;
input wbs1_rty_o;
 
wire [1:0] slave_sel; // One bit per slave
 
// WB Slave 2
output [wb_adr_width-1:0] wbs2_adr_i;
output [wb_dat_width-1:0] wbs2_dat_i;
output [3:0] wbs2_sel_i;
output wbs2_we_i;
output wbs2_cyc_i;
output wbs2_stb_i;
output [2:0] wbs2_cti_i;
output [1:0] wbs2_bte_i;
input [wb_dat_width-1:0] wbs2_dat_o;
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
 
wire [2:0] slave_sel; // One bit per slave
 
reg watchdog_err;
`ifdef ARBITER_IBUS_WATCHDOG
212,6 → 247,10
reg wbs1_ack_o_r;
reg wbs1_err_o_r;
reg wbs1_rty_o_r;
reg [wb_dat_width-1:0] wbs2_dat_o_r;
reg wbs2_ack_o_r;
reg wbs2_err_o_r;
reg wbs2_rty_o_r;
 
wire wbm_ack_i_pre_reg;
 
238,6 → 277,10
wbs1_ack_o_r <= wbs1_ack_o;
wbs1_err_o_r <= wbs1_err_o;
wbs1_rty_o_r <= wbs1_rty_o;
wbs2_dat_o_r <= wbs2_dat_o;
wbs2_ack_o_r <= wbs2_ack_o;
wbs2_err_o_r <= wbs2_err_o;
wbs2_rty_o_r <= wbs2_rty_o;
end // always @ (posedge wb_clk)
 
248,6 → 291,9
assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
slave1_adr;
 
assign slave_sel[2] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
slave2_adr;
 
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o_r;
assign wbs0_dat_i = wbm_dat_o_r;
267,25 → 313,39
assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];
 
assign wbs2_adr_i = wbm_adr_o_r;
assign wbs2_dat_i = wbm_dat_o_r;
assign wbs2_we_i = wbm_dat_o_r;
assign wbs2_sel_i = wbm_sel_o_r;
assign wbs2_cti_i = wbm_cti_o_r;
assign wbs2_bte_i = wbm_bte_o_r;
assign wbs2_cyc_i = wbm_cyc_o_r & slave_sel[1];
assign wbs2_stb_i = wbm_stb_o_r & slave_sel[1];
 
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
assign wbm_dat_i = slave_sel[2] ? wbs2_dat_o_r :
slave_sel[1] ? wbs1_dat_o_r :
wbs0_dat_o_r ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
(slave_sel[1] & wbs1_ack_o_r)
;
(slave_sel[1] & wbs1_ack_o_r) |
(slave_sel[2] & wbs2_ack_o_r);
assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
(slave_sel[1] & wbs1_err_o_r) |
(slave_sel[2] & wbs2_err_o_r) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
(slave_sel[1] & wbs1_rty_o_r);
(slave_sel[1] & wbs1_rty_o_r) |
(slave_sel[2] & wbs2_rty_o_r);
 
// Non-registered ack
assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
(slave_sel[1] & wbs1_ack_o) |
(slave_sel[2] & wbs2_ack_o);
`else // !`ifdef ARBITER_IBUS_REGISTERING
 
296,6 → 356,10
assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
slave1_adr;
 
assign slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
slave2_adr;
 
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
315,21 → 379,34
assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
 
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
assign wbs2_we_i = wbm_we_o;
assign wbs2_sel_i = wbm_sel_o;
assign wbs2_cti_i = wbm_cti_o;
assign wbs2_bte_i = wbm_bte_o;
assign wbs2_cyc_i = wbm_cyc_o & slave_sel[2];
assign wbs2_stb_i = wbm_stb_o & slave_sel[2];
 
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
assign wbm_dat_i = slave_sel[2] ? wbs2_dat_o :
slave_sel[1] ? wbs1_dat_o :
wbs0_dat_o ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
(slave_sel[1] & wbs1_ack_o) |
(slave_sel[2] & wbs2_ack_o);
assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
(slave_sel[1] & wbs1_err_o) |
(slave_sel[2] & wbs2_err_o) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
(slave_sel[1] & wbs1_rty_o);
(slave_sel[1] & wbs1_rty_o) |
(slave_sel[2] & wbs2_rty_o);
 
`endif

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