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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
- from Rev 67 to Rev 69
- ↔ Reverse comparison
Rev 67 → Rev 69
/eth_defines.v
335,3 → 335,6
|
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
`define ETH_WISHBONE_B3 |
|
// TXBuffer Polling enable |
`define POLL_TXBDS |
/ml501_mc.v
146,7 → 146,7
/* On-chip startup RAM */ |
ml501_startup ml501_startup0 |
( |
.wb_adr_i(wbs_strtup_adr_i[11:2]), |
.wb_adr_i(wbs_strtup_adr_i), |
.wb_stb_i(wbs_strtup_stb_i), |
.wb_cyc_i(wbs_strtup_cyc_i), |
.wb_we_i(wbs_strtup_we_i), |
158,6 → 158,7
.wb_rst(wb_rst) |
); |
defparam ml501_startup0.mem_span = startup_size; |
defparam ml501_startup0.adr_width = `ML501_MEMORY_STARTUP_ADDR_WIDTH; |
`else // !`ifdef ML501_MEMORY_STARTUP |
assign wbs_strtup_dat_o = 0; |
assign wb_strtup_ack_o = 0; |
/ml501_ddr2_wb_if.v
8,6 → 8,8
//// To Do: //// |
//// Increase usage of cache BRAM to maximum (currently only //// |
//// 256 bytes out of about 8192) //// |
//// Make this a Wishbone B3 registered feedback burst friendly //// |
//// server. //// |
//// //// |
//// Author(s): //// |
//// - Julius Baxter, julius.baxter@orsoc.se //// |
211,11 → 213,6
always @(posedge wb_clk) |
wb_req_new_r <= wb_req_new; |
|
// Register request address, actually, don't bother, it's useless. |
always @(posedge wb_clk) |
if (wb_req_new) |
wb_req_cache_word_addr <= wb_adr_i[4:2]; |
|
// Register whether it's a hit or not |
// As more lines are added, add them to this check. |
always @(posedge wb_clk) |
265,7 → 262,8
// 1. Enable on first access, if it's not a write |
// 2. Enable if we've just refreshed the cache |
// 3. Enable on ACK'ing for a write |
assign wb_cache_en = (wb_req_new & !wb_we_i) | do_readfrom_finished | |
assign wb_cache_en = (wb_req_new & !wb_we_i) | do_readfrom_finished | |
(wb_req_addr_hit & wb_stb_i & !wb_we_i & !wb_ack_o) | |
(wb_ack_o & wb_we_i); |
|
// Writeback detect logic |
/ml501_startup.v
38,24 → 38,31
//// //// |
////////////////////////////////////////////////////////////////////// |
|
/* Memory containing memory addresses 0-0x200 */ |
/* Memory containing memory addresses 0x0 up to mem_span */ |
module ml501_startup |
( |
input [11:2] wb_adr_i, |
input wb_stb_i, |
input wb_cyc_i, |
input wb_we_i, |
input [3:0] wb_sel_i, |
input [31:0] wb_dat_i, |
output [31:0] wb_dat_o, |
output wb_ack_o, |
input wb_clk, |
input wb_rst |
); |
( wb_adr_i, wb_stb_i, wb_cyc_i, wb_we_i, wb_sel_i, wb_dat_i, |
wb_dat_o, wb_ack_o, |
wb_clk, wb_rst |
); |
|
/* Make this memory span up to this value */ |
parameter mem_span = 12'h800; |
parameter mem_span_word_address_width = 9;// log2((mem_span/bytes_per_word) |
parameter adr_width = 11; // log2(mem_span) |
parameter mem_span_word_address_width = (adr_width-2); |
|
input [adr_width-1:0] wb_adr_i; |
input wb_stb_i; |
input wb_cyc_i; |
input wb_we_i; |
input [3:0] wb_sel_i; |
input [31:0] wb_dat_i; |
output [31:0] wb_dat_o; |
output wb_ack_o; |
input wb_clk; |
input wb_rst; |
|
|
|
// synthesis attribute ram_style of mem is block |
reg [31:0] mem [0:(mem_span/4)-1] /* synthesis ram_style = no_rw_check */; |
reg [mem_span_word_address_width-1:0] adr; |
/ml501_defines.v
20,7 → 20,7
// |
// Main memory options (select only of the following): |
// |
// On-Chip Xilinx RAMBs (~64KByte, resource used depending) |
// On-Chip Xilinx RAMBs (~64KByte, resource use depending) |
// ZBT SSRAM (1MByte, 200Mhz) |
// DDR2 SDRAM (256MByte, 266Mhz) |
// It is recommended the startup memory is used with only the ZBT SSRAM or DDR2 |
32,8 → 32,16
// Use on-chip memory as a boot-ROM |
`define ML501_MEMORY_STARTUP |
`ifdef ML501_MEMORY_STARTUP |
// Define the size of the onchip memory |
`define ML501_MEMORY_STARTUP_ADDR_SPAN 12'h800 |
// Define the size of the onchip low/startup memory |
// 4KByte |
//`define ML501_MEMORY_STARTUP_ADDR_SPAN 16'h1000 |
//`define ML501_MEMORY_STARTUP_ADDR_WIDTH 12 |
// 8KByte |
//`define ML501_MEMORY_STARTUP_ADDR_SPAN 16'h2000 |
//`define ML501_MEMORY_STARTUP_ADDR_WIDTH 13 |
// 32KByte |
`define ML501_MEMORY_STARTUP_ADDR_SPAN 16'h8000 |
`define ML501_MEMORY_STARTUP_ADDR_WIDTH 15 |
`endif |
|
// Main memory configuration |
/ml501.v
113,8 → 113,11
output dbg_tdo_pad_o, |
|
// Uart |
input uart0_srx_pad_i, |
output uart0_stx_pad_o, |
input uart0_RX, |
output uart0_TX, |
// Duplicates of the UART signals, this time to the USB debug cable |
input uart0_RX_expheader, |
output uart0_TX_expheader, |
|
// GPIO |
inout [25:0] gpio |
744,6 → 747,13
|
assign wbs_mc_m_err_o = 1'b0; |
|
// Wires for duplication |
wire uart_rx, uart_tx; |
assign uart_rx = uart0_RX & uart0_RX_expheader; |
|
assign uart0_TX = uart_tx; |
assign uart0_TX_expheader = uart_tx; |
|
uart_top |
#( 32, 5) |
i_uart_0_top |
759,8 → 769,8
.wb_clk_i (wb_clk), |
.wb_rst_i (wb_rst), |
.int_o (uart0_irq), |
.srx_pad_i (uart0_srx_pad_i), |
.stx_pad_o (uart0_stx_pad_o), |
.srx_pad_i (uart_rx), |
.stx_pad_o (uart_tx), |
.cts_pad_i (1'b0), |
.rts_pad_o ( ), |
.dtr_pad_o ( ), |
769,6 → 779,8
.ri_pad_i (1'b0) |
); |
|
|
|
`ifdef USE_ETHERNET |
|
wire phy_smi_data_i, phy_smi_data_o, phy_smi_data_dir; |