URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw
- from Rev 69 to Rev 412
- ↔ Reverse comparison
Rev 69 → Rev 412
/board.h
File deleted
/bootrom/Makefile
0,0 → 1,27
# Makefile for bootROM Verilog |
# We will do it by building the main one, and applying our local board's |
# settings. |
# To rebuild after board.h is changed, a clean must be done first. |
|
# Set the path to our board's root directory |
BOARD_SW_ROOT=.. |
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include $(BOARD_SW_ROOT)/Makefile.inc |
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all: bootrom.v |
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# Copy the one build in the root software path to here. |
bootrom.v: $(SW_ROOT)/bootrom/bootrom.v |
$(Q)cp -v $< . |
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export BOARD_PATH |
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# Pass BOARD_PATH so the Make script in the root software path knows we're to |
# use our board.h file, not theirs. |
$(SW_ROOT)/bootrom/bootrom.v: |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v |
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clean: |
$(Q)rm -f *.o *.bin *.hex *.in *.dis *.v |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean |
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/Makefile.inc
0,0 → 1,26
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# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're |
# in the board's software root path is. |
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# Root from the board's sw/ path |
PROJ_ROOT=../../../.. |
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# Figure out actual path the common software directory |
SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw |
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# Set the BOARD_PATH to point to the root of this board build |
BOARD_PATH=$(shell pwd)/$(BOARD_SW_ROOT)/.. |
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# Set RTL_VERILOG_INCLUDE_DIR so software |
RTL_VERILOG_INCLUDE_DIR=$(BOARD_PATH)/rtl/verilog/include |
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# Set the processor capability flags |
# This doesn't work! :-( Need to figure out way to set these and have them |
# carry through to things like the liborpsoc driver modules etc. |
#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float |
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float |
#export MARCH_FLAGS |
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# Finally include the main software include file |
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include $(SW_ROOT)/Makefile.inc |
/board/include/board.h
0,0 → 1,60
#ifndef _BOARD_H_ |
#define _BOARD_H_ |
|
#define IN_CLK 50000000 // Hz |
//#define IN_CLK 32000000 // Hz |
//#define IN_CLK 30000000 // HZ |
//#define IN_CLK 24000000 // HZ |
//#define IN_CLK 20000000 // HZ |
//#define IN_CLK 18000000 // HZ |
//#define IN_CLK 16000000 // HZ |
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// |
// ROM bootloader |
// |
// Uncomment the appropriate bootloader define. This will effect the bootrom.S |
// file, which is compiled and converted into Verilog for inclusion at |
// synthesis time. See bootloader/bootloader.S for details on each option. |
|
//#define BOOTROM_SPI_FLASH |
#define BOOTROM_GOTO_RESET |
//#define BOOTROM_LOOP_AT_ZERO |
//#define BOOTROM_LOOP_IN_ROM |
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// |
// Defines for each core (memory map base, OR1200 interrupt line number, etc.) |
// |
#define SDRAM_BASE 0x0 |
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#define GPIO_0_BASE 0x91000000 |
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#define UART0_BASE 0x90000000 |
#define UART0_IRQ 2 |
#define UART0_BAUD_RATE 115200 |
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#define SPI0_BASE 0xb0000000 |
#define SPI0_IRQ 6 |
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#define I2C_0_BASE 0xa0000000 |
#define I2C_0_IRQ 10 |
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#define I2C_1_BASE 0xa1000000 |
#define I2C_1_IRQ 11 |
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#define ETH0_BASE 0x92000000 |
#define ETH0_IRQ 4 |
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#define ETH_MACADDR0 0x00 |
#define ETH_MACADDR1 0x12 |
#define ETH_MACADDR2 0x34 |
#define ETH_MACADDR3 0x56 |
#define ETH_MACADDR4 0x78 |
#define ETH_MACADDR5 0x9a |
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// |
// OR1200 tick timer period define |
// |
#define TICKS_PER_SEC 100 |
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#endif |