URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501
- from Rev 492 to Rev 496
- ↔ Reverse comparison
Rev 492 → Rev 496
/rtl/verilog/clkgen/clkgen.v
144,8 → 144,8
defparam dcm0.CLKFX_MULTIPLY = 4; |
defparam dcm0.CLKFX_DIVIDE = 3; |
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// Generate 50 MHz from CLKDV |
defparam dcm0.CLKDV_DIVIDE = 4.0; |
// Generate 66 MHz from CLKDV |
defparam dcm0.CLKDV_DIVIDE = 3.0; |
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BUFG dcm0_clk0_bufg |
(// Outputs |
/rtl/verilog/include/uart_defines.v
246,5 → 246,9
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd11 |
// 50MHz: prescaler 27.1 |
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd27 |
// 66MHz: prescaler 36.1 |
`define PRESCALER_HIGH_PRESET 8'd0 |
`define PRESCALER_LOW_PRESET 8'd27 |
`define PRESCALER_LOW_PRESET 8'd36 |
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/backend/par/bin/ml501.ucf
941,11 → 941,11
NET "eth0_col" IOBDELAY=NONE; |
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## # Timing ignores (to specify unconstrained paths) |
#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock |
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; |
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; |
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; |
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; |
NET "wb_clk" TNM_NET = "wb_clk_grp"; # Wishbone clock |
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "wb_clk_grp" TIG; |
TIMESPEC "TS_OPB_PHYTX" = FROM "wb_clk_grp" TO "TXCLK_GRP" TIG; |
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "wb_clk_grp" TIG; |
TIMESPEC "TS_OPB_PHYRX" = FROM "wb_clk_grp" TO "RXCLK_GRP" TIG; |
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## #------------------------------------------------------------------------------ |
## # IO Pad Location Constraints / Properties for AC97 Sound Controller |
/sw/board/include/board.h
1,7 → 1,8
#ifndef _BOARD_H_ |
#define _BOARD_H_ |
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#define IN_CLK 50000000 // Hz |
//#define IN_CLK 50000000 // Hz |
#define IN_CLK 66666667 // Hz |
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// |
// ROM bootloader |