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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800
    from Rev 568 to Rev 638
    ↔ Reverse comparison
  •

Rev 568 → Rev 638

/Makefile.inc
21,19 → 21,12
include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc
include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc
 
# Check that the XILINX_PATH variable is set
ifeq ($(XILINX_PATH),)
$(error XILINX_PATH environment variable not set. Set it and rerun)
# Check that the Xilinx scripts have been sourced
ifndef XILINX
$(error The XILINX environment variable was not set, \
please run: 'source /path/to/xilinx_ise/settings{32|64}.sh')
endif
 
#XILINX_SETTINGS_SCRIPT ?=/opt/xilinx/13.1/ISE_DS/settings32.sh
# ISE 13.1 ISE_DS version
XILINX_SETTINGS_SCRIPT ?=$(XILINX_PATH)/ISE_DS/settings32.sh
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
$(error XILINX_SETTINGS_SCRIPT variable not set correctly. Cannot find $(XILINX_SETTINGS_SCRIPT))
endif
 
# Backend directories
# This one is the board build's backend dir.
BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend
42,7 → 35,7
# Technology backend (vendor-specific)
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
# This path is for the technology library
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX_PATH)/ISE/verilog
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX)/verilog
 
# Bootrom setup
# BootROM code, which generates a verilog array select values
/backend/par/bin/Makefile
77,67 → 77,56
 
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE)
@echo; echo "\t#### Running NGDBuild ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \
$(NGC_FILE) $@ )
$(Q)ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) \
-uc $(UCF_FILE) $(NGC_FILE) $@
 
#This target uses Xilinx tools to perform Mapping
$(MAPPED_NCD): $(NGD_FILE)
@echo; echo "\t#### Mapping ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
export XIL_MAP_NO_DSP_AUTOREG=1 && \
$(Q) export XIL_MAP_NO_DSP_AUTOREG=1 && \
export XIL_MAP_ALLOW_ANY_DLL_INPUT=1 && \
map -p $(FPGA_PART) -detail -pr b -cm ${XILINX_AREA_TARGET} \
-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE))
-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)
 
#This target uses Xilinx tools to Place & Route the design
$(PARRED_NCD): $(MAPPED_NCD)
@echo; echo "\t#### PAR'ing ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE) )
$(Q)par -w -ol high $(XILINX_FLAGS) $< $@ $(PCD_FILE)
 
#This target uses Xilinx tools to generate a bitstream for download
$(BIT_FILE): $(PARRED_NCD)
@echo; echo "\t#### Generating .bit file ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ )
$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@
 
$(BIT_FILE_FOR_SPI): $(PARRED_NCD)
@echo; echo "\t#### Generating .bit file for SPI load ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ )
$(Q)bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@
 
# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined.
ifeq ($(BOOTLOADER_BIN),)
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
@echo; echo "\t#### Generating .mcs file for SPI load ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< )
$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $<
else
$(MCS_FILE): $(BIT_FILE_FOR_SPI)
@echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####";
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \
)
$(Q)promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \
-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN)
endif
 
#this target downloads the bitstream to the target fpga
download: $(BIT_FILE) $(BATCH_FILE)
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
impact -batch $(BATCH_FILE) )
$(Q)impact -batch $(BATCH_FILE)
 
#This target uses netgen to make a simulation netlist
netlist: $(PARRED_NCD)
@echo; echo "\t#### Generating netlist ####";
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<)
$(Q)netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<
 
#This one uses TRCE to make a timing report
timingreport: $(PARRED_NCD)
@echo; echo "\t#### Generating timing report ####";
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \
trce $(TIMING_REPORT_OPTIONS) $< )
$(Q)trce $(TIMING_REPORT_OPTIONS) $<
 
 
clean:
/syn/xst/bin/Makefile
150,7 → 150,7
# XST command
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
$(Q)echo; echo "\t#### Running XST ####"; echo;
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
$(Q)xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS)
$(Q)echo
 
netlist: $(NETLIST_FILE)
158,8 → 158,7
# Netlist generation command
$(NETLIST_FILE): $(NGC_FILE)
$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
$(Q)netgen -sim -aka -dir . -ofmt verilog $< -w $@
 
 
clean:

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