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/openrisc/trunk/orpsocv2/boards/xilinx
- from Rev 628 to Rev 629
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Rev 628 → Rev 629
/atlys/sim/bin/atlys-or1ksim.cfg
0,0 → 1,270
/* atlys-or1ksim.cfg -- Simulator configuration script file for Atlys board. |
|
Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org |
Copyright (C) 2010, Embecosm Limited |
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
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This file is part of OpenRISC 1000 Architectural Simulator. |
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This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
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This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
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/* -------------------------------------------------------------------------- */ |
/* The Ork1sim has various parameters, that can be set in configuration files |
like this one. The user can specify a configuration file at startup with |
the -f <filename.cfg> option. |
|
The user guide (see the 'doc' directory) gives full details on |
configuration files. This is a reference configuration, which may be used |
as a starting point for customization. |
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A number of peripherals are mapped at standard addresses (above 0x80000000) |
in the Verilog RTL of ORPSoC standard sitribution. The same values should |
be used in Or1ksim section definitions to match the behavior of the Verilog |
|
0x90000000 UART |
0x91000000 GPIO |
0x92000000 Ethernet |
*/ |
/* -------------------------------------------------------------------------- */ |
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/* Simulator section |
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verbose = 0|1 |
debug = 0-9 |
profile = 0|1 |
prof_file = "<filename>" (default: "sim.profile") |
mprofile = 0|1 |
mprof_file = "<filename>" (default: "sim.mprofile") |
history = 0|1 |
exe_log = 0|1 |
exe_log_type = hardware|simple|software|default |
exe_log_start = <value> (default: 0) |
exe_log_end = <value> (default: never end) |
exe_log_marker = <value> (default: no markers) |
exe_log_file = "<filename>" (default: "executed.log") |
exe_bin_insn_log = 0|1 |
exe_bin_insn_log_file = "<filename>" (default: "exe-insn.bin") |
clkcycle = <value>[ps|ns|us|ms] |
*/ |
section sim |
clkcycle = 20ns |
end |
|
/* CPU section |
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ver = <value> (default: 0) |
cfg = <value> (default: 0) |
rev = <value> (default: 0) |
upr = <value> (see user manual for default settings) |
cfgr = <value> (default: 0x00000020) |
sr = <value> (default: 0x00008001) |
superscalar = 0|1 |
hazards = 0|1 |
dependstats = 0|1 |
sbuf_len = <value> (default: 0) |
hardfloat = 0|1 |
*/ |
section cpu |
ver = 0x12 |
cfg = 0x00 |
rev = 0x0001 |
end |
|
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/* Memory section |
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type = unknown|random|unknown|pattern |
random_seed = <value> (default: -1) |
pattern = <value> (default: 0) |
baseaddr = <hex_value> (default: 0) |
size = <hex_value> (default: 1024) |
name = "<string>" (default: "anonymous memory block") |
ce = <value> (default: -1) |
mc = <value> (default: 0) |
delayr = <value> (default: 1) |
delayw = <value> (default: 1) |
log = "<filename>" (default: NULL) |
*/ |
section memory |
name = "RAM" |
type = unknown |
baseaddr = 0x00000000 |
size = 0x08000000 |
delayr = 1 |
delayw = 1 |
end |
|
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/* Data MMU section |
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enabled = 0|1 |
nsets = <value> (default: 1) |
nways = <value> (default: 1) |
pagesize = <value> (default: 8192) |
entrysize = <value> (default: 1) |
ustates = <value> (default: 1) |
hitdelay = <value> (default: 1) |
missdelay = <value> (default: 1) |
*/ |
section dmmu |
enabled = 1 |
nsets = 64 |
nways = 1 |
pagesize = 8192 |
hitdelay = 0 |
missdelay = 0 |
end |
|
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/* Instruction MMU section |
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enabled = 0|1 |
nsets = <value> (default: 1) |
nways = <value> (default: 1) |
pagesize = <value> (default: 8192) |
entrysize = <value> (default: 1) |
ustates = <value> (default: 1) |
hitdelay = <value> (default: 1) |
missdelay = <value> (default: 1) |
*/ |
section immu |
enabled = 1 |
nsets = 64 |
nways = 1 |
pagesize = 8192 |
hitdelay = 0 |
missdelay = 0 |
end |
|
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/* Data cache section |
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enabled = 0|1 |
nsets = <value> (default: 1) |
nways = <value> (default: 1) |
blocksize = <value> (default: 16) |
ustates = <value> (default: 2) |
load_hitdelay = <value> (default: 2) |
load_missdelay = <value> (default: 2) |
store_hitdelay = <value> (default: 0) |
store_missdelay = <value> (default: 0) |
*/ |
|
section dc |
enabled = 1 |
nsets = 32768 |
nways = 1 |
blocksize = 32 |
load_hitdelay = 0 |
load_missdelay = 0 |
store_hitdelay = 0 |
store_missdelay = 0 |
end |
|
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/* Instruction cache section |
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enabled = 0|1 |
nsets = <value> (default: 1) |
nways = <value> (default: 1) |
blocksize = <value> (default: 16) |
ustates = <value> (default: 2) |
hitdelay = <value> (default: 1) |
missdelay = <value> (default: 1) |
*/ |
section ic |
enabled = 1 |
nsets = 32768 |
nways = 1 |
blocksize = 32 |
hitdelay = 0 |
missdelay = 0 |
end |
|
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/* Programmable interrupt controller section |
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enabled = 0|1 |
edge_trigger = 0|1 (default: 1) |
*/ |
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section pic |
enabled = 1 |
end |
|
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/* Power management section |
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enabled = 0|1 |
*/ |
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section pm |
enabled = 0 |
end |
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/* Debug unit section |
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enabled = 0|1 |
rsp_enabled = 0|1 |
rsp_port = <value> (default: 51000) |
vapi_id = <value> (default: 0) |
*/ |
section debug |
enabled = 0 |
end |
|
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/* UART section |
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enabled = 0|1 |
baseaddr = <value> (default: 0) |
channel = "value>" (default: "xterm:") |
irq = <value> (default: 0) |
16550 = 0|1 |
jitter = <value> (default: 0) |
vapi_id = <value> (default: 0) |
*/ |
|
section uart |
enabled = 1 |
baseaddr = 0x90000000 |
irq = 2 |
16550 = 1 |
end |
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/* Ethernet section |
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enabled = 0|1 |
baseaddr = <value> (default: 0) |
dma = <value> (default: 0) |
irq = <value> (default: 0) |
rtx_type = 0|1 |
rx_channel = <value> (default: 0) |
tx_channel = <value> (default: 0) |
rxfile = "<filename>" (default: "eth_rx") |
txfile = "<filename>" (default: "eth_rx") |
sockif = "<service>" (default: "or1ksim_eth") |
vapi_id = <value> (default: 0) |
*/ |
section ethernet |
enabled = 1 |
baseaddr = 0x92000000 |
irq = 4 |
rtx_type = "tap" |
tap_dev = "tap0" |
dummy_crc = 1 |
end |