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    /openrisc/trunk/orpsocv2/boards
    from Rev 409 to Rev 411
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  •

Rev 409 → Rev 411

/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
52,7 → 52,7
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
 
`ifdef RTL_SIM
`ifdef eth_IS_GATELEVEL
`ifdef ethmac_IS_GATELEVEL
`define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
`define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
`else
72,8 → 72,15
integer lfsr_last_byte;
 
// Is number of ethernet packets to send if doing the eth-rx test.
parameter eth_stim_num_rx_only_tests = 256;
parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
parameter eth_stim_num_rx_only_packet_size = 512;
parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
parameter eth_stim_num_rx_only_IPG = 800000; // ns
 
// Do call/response test
reg eth_stim_do_rx_reponse_to_tx;
 
parameter num_tx_bds = 16;
parameter num_tx_bds_mask = 4'hf;
80,6 → 87,7
parameter num_rx_bds = 16;
parameter num_rx_bds_mask = 4'hf;
parameter max_eth_packet_size = 16'h0600;
 
// If running eth-rxtxbig test (sending and receiving maximum packets), then
// set this parameter to the max packet size, otherwise min packet size
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
140,7 → 148,11
lfsr_last_byte = 0;
eth_stim_waiting = 1;
expected_rxbd = num_tx_bds; // init this here
 
eth_stim_do_rx_reponse_to_tx = 0;
while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
begin
#100;
149,14 → 161,26
begin
if (eth_inject_errors)
begin
do_rx_only_stim(16, 0, 0);
do_rx_only_stim(128, 1'b1, 8);
do_rx_only_stim(256, 1'b1, 4);
do_rx_only_stim(16, 64, 0, 0);
do_rx_only_stim(128, 64, 1'b1, 8);
do_rx_only_stim(256, 64, 1'b1, 4);
eth_stim_waiting = 0;
end
else
begin
do_rx_only_stim(eth_stim_num_rx_only_tests, 0, 0);
//do_rx_only_stim(eth_stim_num_rx_only_num_packets,
//eth_stim_num_rx_only_packet_size, 0, 0);
 
// Call packet send loop directly. No error injection.
send_packet_loop(eth_stim_num_rx_only_num_packets,
eth_stim_num_rx_only_packet_size,
eth_stim_num_rx_only_packet_size_change,
eth_stim_num_rx_only_packet_size_change_amount,
eth_phy0.eth_speed, // Speed
eth_stim_num_rx_only_IPG, // IPG
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
0, 0);
eth_stim_waiting = 0;
end
end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
163,8 → 187,26
// If both RX and TX enabled
else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
begin
// If RX enable and TX enable
do_rx_while_tx_stim(1400);
// Both enabled - let's wait for the first packet transmitted
// to see what stimulus we should provide
while (num_tx_packets==1)
#1000;
 
$display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
// Check the first received byte's value
case (eth_phy0.tx_mem[0])
0:
begin
// kickoff call/response here
eth_stim_do_rx_reponse_to_tx = 1;
end
default:
begin
do_rx_while_tx_stim(1400);
end
endcase // case (eth_phy0.tx_mem[0])
eth_stim_waiting = 0;
end
end // while (eth_stim_waiting)
175,16 → 217,17
// Sends a set of packets at both speeds
task do_rx_only_stim;
input [31:0] num_packets;
input [31:0] start_packet_size;
input inject_errors;
input [31:0] inject_errors_mod;
begin
expected_rxbd = num_tx_bds; // init this here
for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
begin
send_packet_loop(num_packets, 64, 2'b01, 1, speed_loop[0], 10000,
send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
speed_loop[0], 10000,
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
inject_errors, inject_errors_mod);
202,7 → 245,6
integer j;
begin
expected_rxbd = num_tx_bds; // init this here
for(j=0;j<num_packets;j=j+1)
begin
269,32 → 311,103
end
endtask // do_rx_stim
 
// Registers used in detecting transmitted packets
reg eth_stim_tx_loop_keep_polling;
reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
reg eth_stim_detected_packet_tx;
 
// If in call-response mode, whenever we receive a TX packet, we generate
// one and send it back
always @(negedge eth_stim_detected_packet_tx)
begin
if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
// Continue if we are enabled
do_rx_response_to_tx();
end
// Generate RX packet in rsponse to TX packet
task do_rx_response_to_tx;
//input unused;
reg [31:0] IPG; // Inter-packet gap
reg [31:0] packet_size;
integer j;
begin
 
// Get packet size test wants us to send
packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
 
IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
$display("do_rx_response_to_tx IPG = %0d", IPG);
if (packet_size == 0)
begin
// Constrained random sized packets
packet_size = $random;
while (packet_size > (max_eth_packet_size-4))
packet_size = packet_size / 2;
if (packet_size < 60)
packet_size = packet_size + 60;
end
$display("do_rx_response_to_tx packet_size = %0d", packet_size);
send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
IPG, 48'h0012_3456_789a,
48'h0708_090A_0B0C, 1, 1'b0, 0);
// If RX enable went low, wait for it go high again
if (ethmac_rxen===1'b0)
begin
while (ethmac_rxen===1'b0)
begin
@(posedge ethmac_rxen);
#10000;
end
// RX disabled and when re-enabled we reset the buffer
// descriptor number
expected_rxbd = num_tx_bds;
 
end
 
end
endtask // do_rx_response_to_tx
 
//
// always@() to check the TX buffer descriptors
//
reg keep_polling;
reg [31:0] txbd_lenstat, last_txbd_lenstat;
reg detected_packet_tx;
always @(posedge ethmac_txen)
begin
last_txbd_lenstat = 0;
keep_polling=1;
ethmac_last_txbd_lenstat = 0;
eth_stim_tx_loop_keep_polling=1;
// Wait on the TxBD Ready bit
while(keep_polling)
while(eth_stim_tx_loop_keep_polling)
begin
#10;
get_bd_lenstat(expected_txbd, txbd_lenstat);
get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
// Check if we've finished transmitting this BD
if (!txbd_lenstat[15] & last_txbd_lenstat[15])
if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
// Falling edge of TX BD Ready
detected_packet_tx = 1;
eth_stim_detected_packet_tx = 1;
 
last_txbd_lenstat = txbd_lenstat;
ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
// If TX en goes low then exit
if (!ethmac_txen)
keep_polling = 0;
else if (detected_packet_tx)
eth_stim_tx_loop_keep_polling = 0;
else if (eth_stim_detected_packet_tx)
begin
// Wait until the eth_phy has finished receiving it
while (eth_phy0.mtxen_i === 1'b1)
301,10 → 414,10
#10;
$display("(%t) Check TX packet: bd %d: 0x%h",$time,
expected_txbd, txbd_lenstat);
expected_txbd, ethmac_txbd_lenstat);
 
// Check the TXBD, see if the packet transmitted OK
if (txbd_lenstat[8] | txbd_lenstat[3])
if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
begin
// Error occured
`TIME;
311,10 → 424,10
$display("*E TX Error of packet %0d detected.",
num_tx_packets);
$display(" TX BD %0d = 0x%h", expected_txbd,
txbd_lenstat);
if (txbd_lenstat[8])
ethmac_txbd_lenstat);
if (ethmac_txbd_lenstat[8])
$display(" Underrun in MAC during TX");
if (txbd_lenstat[3])
if (ethmac_txbd_lenstat[3])
$display(" Retransmission limit hit");
$finish;
321,8 → 434,8
end
else
begin
// Packet was OK, let's compare the contents we received
// with those that were meant to be transmitted
// Packet was OK, let's compare the contents we
// received with those that were meant to be transmitted
if (eth_stim_check_tx_packet_contents)
begin
check_tx_packet(expected_txbd);
329,11 → 442,11
expected_txbd = (expected_txbd + 1) &
num_tx_bds_mask;
num_tx_packets = num_tx_packets + 1;
detected_packet_tx = 0;
eth_stim_detected_packet_tx = 0;
end
end
end
end // while (keep_polling)
end // while (eth_stim_tx_loop_keep_polling)
end // always @ (posedge ethmac_txen)
 
348,7 → 461,8
reg [7:0] phy_byte;
reg [31:0] txpnt_wb; // Pointer in array to where data should be
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM part
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM
// part
reg [21:0] buffer;
reg [7:0] sdram_byte;
reg [31:0] tx_len_bd;
453,7 → 567,12
begin
error_type = 0;
error_this_time = 0;
 
if (num_packets == 0)
// Loop forever when num_packets is 0
num_packets = 32'h7fffffff;
if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
begin
// write to phy's control register for 100Mbps
712,7 → 831,9
endtask // set_rx_addr_type
 
 
`ifdef eth_IS_GATELEVEL // Check if we're using a synthesized version of eth module
// Check if we're using a synthesized version of eth module
`ifdef ethmac_IS_GATELEVEL
 
// Get the length/status register of the ethernet buffer descriptor
task get_bd_lenstat;
input [31:0] bd_num;// Number of ethernet BD to check
778,7 → 899,7
end
endtask // get_bd_addr
 
`else // !`ifdef eth_IS_GATELEVEL
`else // !`ifdef ethmac_IS_GATELEVEL
// Get the length/status register of the ethernet buffer descriptor
task get_bd_lenstat;
806,12 → 927,14
always @*
begin
// Loop here waiting for a packet to be sent, or if we shouldn't
// check them at all.
// Loop here until:
// 1 - packets sent is not equal to packets checked (ie. some to check)
// 2 - we're explicitly disabled for some reason
// 3 - Receive has been disabled in the MAC
while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
!eth_stim_check_rx_packet_contents)
!eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
#1000;
 
eth_rx_packet_length_to_check
= rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
899,9 → 1022,9
 
if (phy_byte !== sdram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of RX packet! phy = %h, ram = %h",
i, phy_byte, sdram_byte);
// `TIME;
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
failure = 1;
end
 
/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v
487,15 → 487,11
.Dqm (sdram_dqm_pad_o_to_sdram));
`endif // `ifdef VERSATILE_SDRAM
 
initial
`ifdef VCD
reg vcd_go = 0;
always @(vcd_go)
begin
`ifndef SIM_QUIET
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`endif
`ifdef VCD
`ifdef VCD_DELAY
#(`VCD_DELAY);
`endif
522,9 → 518,22
`define VCD_DEPTH 0
`endif
$dumpvars(`VCD_DEPTH);
end
`endif // `ifdef VCD
initial
begin
`ifndef SIM_QUIET
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`endif
`ifdef VCD
vcd_go = 1;
`endif
end // initial begin
end // initial begin
`ifdef END_TIME
initial begin
/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v
39,130 → 39,135
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
wire direction;
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
`endif
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
reg direction;
`endif
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
`endif
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
// async FIFO with multiple queues
 
module async_fifo_mq (
298,7 → 303,7
input we_b;
input clk_a, clk_b;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
3474,10 → 3479,9
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
 
//`define MT48LC32M16 // 64MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
 
// Define this to allow indication that a burst read is still going
// to the wishbone state machine, so it doesn't start emptying the
3493,7 → 3497,7
 
 
`ifdef MT48LC32M16
// using 1 of MT48LC16M16
// using 1 of MT48LC32M16
// SDRAM data width is 16
`define SDRAM_DATA_WIDTH 16
4100,6 → 4104,11
 
endmodule
`endif // !`ifdef ORIGINAL_EGRESS_FIFO
// true dual port RAM, sync
 
`ifdef ACTEL
`define SYN
`endif
module vfifo_dual_port_ram_dc_sw
(
d_a,
4119,7 → 4128,7
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0]/*synthesis syn_ramstyle = "no_rw_check"*/ ;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v
1072,7 → 1072,7
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
/actel/ordb1a3pe1500/sim/bin/Makefile
134,6 → 134,10
# This path is for the technology library
TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
 
# Synthesis directory for board
BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
 
# System software dir
COMMON_SW_DIR=$(PROJECT_ROOT)/sw
BOARD_SW_DIR=$(BOARD_DIR)/sw
208,6 → 212,11
#
# Verilog DUT source variables
#
 
# First consider any modules we'll use gatelevel descriptions of.
# These will have to be set on the command line
GATELEVEL_MODULES ?=
 
# First we get a list of modules in the RTL path of the board's path.
# Next we check which modules not in the board's RTL path are in the root RTL
# path (modules which can be commonly instantiated, but over which board
214,7 → 223,7
# build-specific versions take precedence.)
 
# Paths under board/***/rtl/verilog we wish to exclude when getting modules
BOARD_VERILOG_MODULES_EXCLUDE= include
BOARD_VERILOG_MODULES_EXCLUDE= include $(GATELEVEL_MODULES)
BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
# Apply exclude to list of modules
BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
227,10 → 236,16
# Now get list of modules that we don't have a version of in the board path
COMMON_VERILOG_MODULES_EXCLUDE= include
COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
 
COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
 
 
# Add these to exclude their RTL directories from being included in scripts
 
 
 
# Rule for debugging this script
print-common-modules-exclude:
@echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
355,6 → 370,10
$(Q)for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(BOARD_RTL_VERILOG_DIR)/$$module >> $@; fi; done
$(Q)for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(COMMON_RTL_VERILOG_DIR)/$$module >> $@; fi; done
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
$(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
echo "+libext+.vm" >> $@; \
fi
$(Q)echo >> $@
 
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
431,9 → 450,6
# Include the test-defines.v generation rule
include $(PROJECT_ROOT)/sim/bin/definesgen.inc
 
# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
# More possible test defines go here
 
#
# Software make rules (called recursively)
#
472,6 → 488,7
.PHONY : sw
sw: $(SIM_SW_IMAGE)
 
 
flash.in: $(SW_TEST_DIR)/$(TEST).flashin
$(Q)if [ -L $@ ]; then unlink $@; fi
$(Q)ln -s $< $@
490,6 → 507,14
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
 
# Create test software disassembly
 
sw-dis: $(SW_TEST_DIR)/$(TEST).dis
$(Q)cp -v $< .
 
$(SW_TEST_DIR)/$(TEST).dis:
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
 
#
# Cleaning rules
#
/actel/ordb1a3pe1500/sw/bootrom/bootrom.v File deleted
/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
120,6 → 120,8
RTL_TOP ?= $(DESIGN_NAME)_top
EDIF_FILE ?=$(RTL_TOP).edn
EDIF_FILE_OUT ?= ../out/$(EDIF_FILE)
VLOG_NETLIST_FILE ?=$(RTL_TOP).vm
VLOG_NETLIST_FILE_OUT ?= ../out/$(VLOG_NETLIST_FILE)
# Synthesis params
#FREQ ?= 50.0000
FREQ ?= 125.000
161,7 → 163,7
 
 
 
all: print-config $(EDIF_FILE_OUT)
all: print-config $(EDIF_FILE_OUT) $(VLOG_NETLIST_FILE_OUT)
 
#create the work dir
$(SYN_WORK_DIR):
305,6 → 307,9
$(EDIF_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE)
cp $^ $@
 
$(VLOG_NETLIST_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(VLOG_NETLIST_FILE)
cp $^ $@
 
clean-all: clean-sw clean clean-edifs
 
clean-sw:

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