URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550
- from Rev 55 to Rev 360
- ↔ Reverse comparison
Rev 55 → Rev 360
/uart_top.v
File deleted
uart_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Makefile
===================================================================
--- Makefile (.../components/uart16550) (revision 55)
+++ Makefile (.../uart16550) (nonexistent)
@@ -1,3 +0,0 @@
-uart_ip:
- cat raminfr.v uart_sync_flops.v uart_regs.v uart_rfifo.v uart_tfifo.v uart_receiver.v uart_transmitter.v uart_debug_if.v uart_wb.v uart_top.v > uart_ip.v
-all: uart_ip
\ No newline at end of file
Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: uart_regs.v
===================================================================
--- uart_regs.v (.../components/uart16550) (revision 55)
+++ uart_regs.v (.../uart16550) (revision 360)
@@ -61,11 +61,7 @@
//
// CVS Revision History
//
-// $Log: uart_regs.v,v $
-// Revision 1.42 2004/11/22 09:21:59 igorm
-// Timeout interrupt should be generated only when there is at least ony
-// character in the fifo.
-//
+// $Log: not supported by cvs2svn $
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
@@ -233,682 +229,682 @@
`define UART_DL2 15:8
module uart_regs (clk,
- wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
+ wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
-// additional signals
- modem_inputs,
- stx_pad_o, srx_pad_i,
+ // additional signals
+ modem_inputs,
+ stx_pad_o, srx_pad_i,
`ifdef DATA_BUS_WIDTH_8
`else
-// debug interface signals enabled
-ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
+ // debug interface signals enabled
+ ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
- rts_pad_o, dtr_pad_o, int_o
+ rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
- , baud_o
+ , baud_o
`endif
- );
+ );
-input clk;
-input wb_rst_i;
-input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
-input [7:0] wb_dat_i;
-output [7:0] wb_dat_o;
-input wb_we_i;
-input wb_re_i;
+ input clk;
+ input wb_rst_i;
+ input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
+ input [7:0] wb_dat_i;
+ output [7:0] wb_dat_o;
+ input wb_we_i;
+ input wb_re_i;
-output stx_pad_o;
-input srx_pad_i;
+ output stx_pad_o;
+ input srx_pad_i;
-input [3:0] modem_inputs;
-output rts_pad_o;
-output dtr_pad_o;
-output int_o;
+ input [3:0] modem_inputs;
+ output rts_pad_o;
+ output dtr_pad_o;
+ output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
-output baud_o;
+ output baud_o;
`endif
`ifdef DATA_BUS_WIDTH_8
`else
-// if 32-bit databus and debug interface are enabled
-output [3:0] ier;
-output [3:0] iir;
-output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
-output [4:0] mcr;
-output [7:0] lcr;
-output [7:0] msr;
-output [7:0] lsr;
-output [`UART_FIFO_COUNTER_W-1:0] rf_count;
-output [`UART_FIFO_COUNTER_W-1:0] tf_count;
-output [2:0] tstate;
-output [3:0] rstate;
+ // if 32-bit databus and debug interface are enabled
+ output [3:0] ier;
+ output [3:0] iir;
+ output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
+ output [4:0] mcr;
+ output [7:0] lcr;
+ output [7:0] msr;
+ output [7:0] lsr;
+ output [`UART_FIFO_COUNTER_W-1:0] rf_count;
+ output [`UART_FIFO_COUNTER_W-1:0] tf_count;
+ output [2:0] tstate;
+ output [3:0] rstate;
`endif
-wire [3:0] modem_inputs;
-reg enable;
+ wire [3:0] modem_inputs;
+ reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
-assign baud_o = enable; // baud_o is actually the enable signal
+ assign baud_o = enable; // baud_o is actually the enable signal
`endif
-wire stx_pad_o; // received from transmitter module
-wire srx_pad_i;
-wire srx_pad;
+ wire stx_pad_o; // received from transmitter module
+ wire srx_pad_i;
+ wire srx_pad;
-reg [7:0] wb_dat_o;
+ reg [7:0] wb_dat_o;
-wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
-wire [7:0] wb_dat_i;
+ wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
+ wire [7:0] wb_dat_i;
-reg [3:0] ier;
-reg [3:0] iir;
-reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
-reg [4:0] mcr;
-reg [7:0] lcr;
-reg [7:0] msr;
-`ifdef UART_FIX_BAUDRATE
- wire [15:0] dl;
- assign dl = 16'h`UART_DIVISOR;
-`else
-reg [15:0] dl; // 32-bit divisor latch
-`endif
-reg [7:0] scratch; // UART scratch register
-reg start_dlc; // activate dlc on writing to UART_DL1
-reg lsr_mask_d; // delay for lsr_mask condition
-reg msi_reset; // reset MSR 4 lower bits indicator
-//reg threi_clear; // THRE interrupt clear flag
-reg [15:0] dlc; // 32-bit divisor latch counter
-reg int_o;
+ reg [3:0] ier;
+ reg [3:0] iir;
+ reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
+ reg [4:0] mcr;
+ reg [7:0] lcr;
+ reg [7:0] msr;
+ reg [15:0] dl; // 32-bit divisor latch
+ reg [7:0] scratch; // UART scratch register
+ reg start_dlc; // activate dlc on writing to UART_DL1
+ reg lsr_mask_d; // delay for lsr_mask condition
+ reg msi_reset; // reset MSR 4 lower bits indicator
+ //reg threi_clear; // THRE interrupt clear flag
+ reg [15:0] dlc; // 32-bit divisor latch counter
+ reg int_o;
-reg [3:0] trigger_level; // trigger level of the receiver FIFO
-reg rx_reset;
-reg tx_reset;
+ reg [3:0] trigger_level; // trigger level of the receiver FIFO
+ reg rx_reset;
+ reg tx_reset;
-wire dlab; // divisor latch access bit
-wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
-wire loopback; // loopback bit (MCR bit 4)
-wire cts, dsr, ri, dcd; // effective signals
-wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
-wire rts_pad_o, dtr_pad_o; // modem control outputs
+ wire dlab; // divisor latch access bit
+ wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
+ wire loopback; // loopback bit (MCR bit 4)
+ wire cts, dsr, ri, dcd; // effective signals
+ wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
+ wire rts_pad_o, dtr_pad_o; // modem control outputs
-// LSR bits wires and regs
-wire [7:0] lsr;
-wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
-reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
-wire lsr_mask; // lsr_mask
+ // LSR bits wires and regs
+ wire [7:0] lsr;
+ wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
+ reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
+ wire lsr_mask; // lsr_mask
-//
-// ASSINGS
-//
+ //
+ // ASSINGS
+ //
-assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
+ assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
-assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
-assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
+ assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
+ assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
-assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
- : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
+ assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
+ : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
-assign dlab = lcr[`UART_LC_DL];
-assign loopback = mcr[4];
+ assign dlab = lcr[`UART_LC_DL];
+ assign loopback = mcr[4];
-// assign modem outputs
-assign rts_pad_o = mcr[`UART_MC_RTS];
-assign dtr_pad_o = mcr[`UART_MC_DTR];
+ // assign modem outputs
+ assign rts_pad_o = mcr[`UART_MC_RTS];
+ assign dtr_pad_o = mcr[`UART_MC_DTR];
-// Interrupt signals
-wire rls_int; // receiver line status interrupt
-wire rda_int; // receiver data available interrupt
-wire ti_int; // timeout indicator interrupt
-wire thre_int; // transmitter holding register empty interrupt
-wire ms_int; // modem status interrupt
+ // Interrupt signals
+ wire rls_int; // receiver line status interrupt
+ wire rda_int; // receiver data available interrupt
+ wire ti_int; // timeout indicator interrupt
+ wire thre_int; // transmitter holding register empty interrupt
+ wire ms_int; // modem status interrupt
-// FIFO signals
-reg tf_push;
-reg rf_pop;
-wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
-wire rf_error_bit; // an error (parity or framing) is inside the fifo
-wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
-wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
-wire [2:0] tstate;
-wire [3:0] rstate;
-wire [9:0] counter_t;
+ // FIFO signals
+ reg tf_push;
+ reg rf_pop;
+ wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
+ wire rf_error_bit; // an error (parity or framing) is inside the fifo
+ wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
+ wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
+ wire [2:0] tstate;
+ wire [3:0] rstate;
+ wire [9:0] counter_t;
-wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
-reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
-reg [7:0] block_value; // One character length minus stop bit
+ wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
+ reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
+ reg [7:0] block_value; // One character length minus stop bit
-// Transmitter Instance
-wire serial_out;
+ // Transmitter Instance
+ wire serial_out;
-uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
+ uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
- // Synchronizing and sampling serial RX input
- uart_sync_flops i_uart_sync_flops
- (
- .rst_i (wb_rst_i),
- .clk_i (clk),
- .stage1_rst_i (1'b0),
- .stage1_clk_en_i (1'b1),
- .async_dat_i (srx_pad_i),
- .sync_dat_o (srx_pad)
- );
- defparam i_uart_sync_flops.width = 1;
- defparam i_uart_sync_flops.init_value = 1'b1;
+ // Synchronizing and sampling serial RX input
+ uart_sync_flops i_uart_sync_flops
+ (
+ .rst_i (wb_rst_i),
+ .clk_i (clk),
+ .stage1_rst_i (1'b0),
+ .stage1_clk_en_i (1'b1),
+ .async_dat_i (srx_pad_i),
+ .sync_dat_o (srx_pad)
+ );
+ defparam i_uart_sync_flops.width = 1;
+ defparam i_uart_sync_flops.init_value = 1'b1;
-// handle loopback
-wire serial_in = loopback ? serial_out : srx_pad;
-assign stx_pad_o = loopback ? 1'b1 : serial_out;
+ // handle loopback
+ wire serial_in = loopback ? serial_out : srx_pad;
+ assign stx_pad_o = loopback ? 1'b1 : serial_out;
-// Receiver Instance
-uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
- counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
+ // Receiver Instance
+ uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
+ counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
-// Asynchronous reading here because the outputs are sampled in uart_wb.v file
-always @(dl or dlab or ier or iir or scratch
- or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
-begin
+ // Asynchronous reading here because the outputs are sampled in uart_wb.v file
+ always @(dl or dlab or ier or iir or scratch
+ or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
+ begin
case (wb_addr_i)
- `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
- `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
- `UART_REG_II : wb_dat_o = {4'b1100,iir};
- `UART_REG_LC : wb_dat_o = lcr;
- `UART_REG_LS : wb_dat_o = lsr;
- `UART_REG_MS : wb_dat_o = msr;
- `UART_REG_SR : wb_dat_o = scratch;
- default: wb_dat_o = 8'b0; // ??
+ `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
+ `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
+ `UART_REG_II : wb_dat_o = {4'b1100,iir};
+ `UART_REG_LC : wb_dat_o = lcr;
+ `UART_REG_LS : wb_dat_o = lsr;
+ `UART_REG_MS : wb_dat_o = msr;
+ `UART_REG_SR : wb_dat_o = scratch;
+ default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
-end // always @ (dl or dlab or ier or iir or scratch...
+ end // always @ (dl or dlab or ier or iir or scratch...
-// rf_pop signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // rf_pop signal handling
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- rf_pop <= #1 0;
+ rf_pop <= 0;
else
- if (rf_pop) // restore the signal to 0 after one clock cycle
- rf_pop <= #1 0;
- else
- if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
- rf_pop <= #1 1; // advance read pointer
-end
+ if (rf_pop) // restore the signal to 0 after one clock cycle
+ rf_pop <= 0;
+ else
+ if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
+ rf_pop <= 1; // advance read pointer
+ end
-wire lsr_mask_condition;
-wire iir_read;
-wire msr_read;
-wire fifo_read;
-wire fifo_write;
+ wire lsr_mask_condition;
+ wire iir_read;
+ wire msr_read;
+ wire fifo_read;
+ wire fifo_write;
-assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
-assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
-assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
-assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
-assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
+ assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
+ assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
+ assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
+ assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
+ assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
-// lsr_mask_d delayed signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // lsr_mask_d delayed signal handling
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- lsr_mask_d <= #1 0;
+ lsr_mask_d <= 0;
else // reset bits in the Line Status Register
- lsr_mask_d <= #1 lsr_mask_condition;
-end
+ lsr_mask_d <= lsr_mask_condition;
+ end
-// lsr_mask is rise detected
-assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
+ // lsr_mask is rise detected
+ assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
-// msi_reset signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // msi_reset signal handling
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- msi_reset <= #1 1;
+ msi_reset <= 1;
else
- if (msi_reset)
- msi_reset <= #1 0;
- else
- if (msr_read)
- msi_reset <= #1 1; // reset bits in Modem Status Register
-end
+ if (msi_reset)
+ msi_reset <= 0;
+ else
+ if (msr_read)
+ msi_reset <= 1; // reset bits in Modem Status Register
+ end
-//
-// WRITES AND RESETS //
-//
-// Line Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- lcr <= #1 8'b00000011; // 8n1 setting
- else
- if (wb_we_i && wb_addr_i==`UART_REG_LC)
- lcr <= #1 wb_dat_i;
+ //
+ // WRITES AND RESETS //
+ //
+ // Line Control Register
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ lcr <= 8'b00000011; // 8n1 setting
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_LC)
+ lcr <= wb_dat_i;
-// Interrupt Enable Register or UART_DL2
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- begin
- ier <= #1 4'b0000; // no interrupts after reset
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL2] <= #1 8'b0;
-`endif
- end
- else
- if (wb_we_i && wb_addr_i==`UART_REG_IE)
- if (dlab)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL2] <= #1 wb_dat_i;
-`endif
- end
- else
- ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
+ // Interrupt Enable Register or UART_DL2
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ begin
+ ier <= 4'b0000; // no interrupts after reset
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET;
+`else
+ dl[`UART_DL2] <= 8'b0;
+`endif
+ end
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_IE)
+ if (dlab)
+ begin
+ dl[`UART_DL2] <=
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL2];
+`else
+ wb_dat_i;
+`endif
+ end
+ else
+ ier <= wb_dat_i[3:0]; // ier uses only 4 lsb
-// FIFO Control Register and rx_reset, tx_reset signals
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) begin
- fcr <= #1 2'b11;
- rx_reset <= #1 0;
- tx_reset <= #1 0;
- end else
- if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
- fcr <= #1 wb_dat_i[7:6];
- rx_reset <= #1 wb_dat_i[1];
- tx_reset <= #1 wb_dat_i[2];
- end else begin
- rx_reset <= #1 0;
- tx_reset <= #1 0;
- end
+ // FIFO Control Register and rx_reset, tx_reset signals
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) begin
+ fcr <= 2'b11;
+ rx_reset <= 0;
+ tx_reset <= 0;
+ end else
+ if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
+ fcr <= wb_dat_i[7:6];
+ rx_reset <= wb_dat_i[1];
+ tx_reset <= wb_dat_i[2];
+ end else begin
+ rx_reset <= 0;
+ tx_reset <= 0;
+ end
-// Modem Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- mcr <= #1 5'b0;
- else
- if (wb_we_i && wb_addr_i==`UART_REG_MC)
- mcr <= #1 wb_dat_i[4:0];
+ // Modem Control Register
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ mcr <= 5'b0;
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_MC)
+ mcr <= wb_dat_i[4:0];
-// Scratch register
-// Line Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- scratch <= #1 0; // 8n1 setting
- else
- if (wb_we_i && wb_addr_i==`UART_REG_SR)
- scratch <= #1 wb_dat_i;
+ // Scratch register
+ // Line Control Register
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ scratch <= 0; // 8n1 setting
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_SR)
+ scratch <= wb_dat_i;
-// TX_FIFO or UART_DL1
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL1] <= #1 8'b0;
-`endif
- tf_push <= #1 1'b0;
- start_dlc <= #1 1'b0;
- end
- else
- if (wb_we_i && wb_addr_i==`UART_REG_TR)
- if (dlab)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL1] <= #1 wb_dat_i;
-`endif
- start_dlc <= #1 1'b1; // enable DL counter
- tf_push <= #1 1'b0;
- end
- else
- begin
- tf_push <= #1 1'b1;
- start_dlc <= #1 1'b0;
- end // else: !if(dlab)
- else
- begin
- start_dlc <= #1 1'b0;
- tf_push <= #1 1'b0;
- end // else: !if(dlab)
+ // TX_FIFO or UART_DL1
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i)
+ begin
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL1] <= `PRESCALER_LOW_PRESET;
+`else
+ dl[`UART_DL1] <= 8'b0;
+`endif
+ tf_push <= 1'b0;
+ start_dlc <= 1'b0;
+ end
+ else
+ if (wb_we_i && wb_addr_i==`UART_REG_TR)
+ if (dlab)
+ begin
+`ifdef PRESCALER_PRESET_HARD
+ dl[`UART_DL1] <= dl[`UART_DL1];
+`else
+ dl[`UART_DL1] <= wb_dat_i;
+`endif
+ start_dlc <= 1'b1; // enable DL counter
+ tf_push <= 1'b0;
+ end
+ else
+ begin
+ tf_push <= 1'b1;
+ start_dlc <= 1'b0;
+ end // else: !if(dlab)
+ else
+ begin
+ start_dlc <= 1'b0;
+ tf_push <= 1'b0;
+ end // else: !if(dlab)
-// Receiver FIFO trigger level selection logic (asynchronous mux)
-always @(fcr)
- case (fcr[`UART_FC_TL])
- 2'b00 : trigger_level = 1;
- 2'b01 : trigger_level = 4;
- 2'b10 : trigger_level = 8;
- 2'b11 : trigger_level = 14;
- endcase // case(fcr[`UART_FC_TL])
-
-//
-// STATUS REGISTERS //
-//
+ // Receiver FIFO trigger level selection logic (asynchronous mux)
+ always @(fcr)
+ case (fcr[`UART_FC_TL])
+ 2'b00 : trigger_level = 1;
+ 2'b01 : trigger_level = 4;
+ 2'b10 : trigger_level = 8;
+ 2'b11 : trigger_level = 14;
+ endcase // case(fcr[`UART_FC_TL])
+
+ //
+ // STATUS REGISTERS //
+ //
-// Modem Status Register
-reg [3:0] delayed_modem_signals;
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // Modem Status Register
+ reg [3:0] delayed_modem_signals;
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
begin
- msr <= #1 0;
- delayed_modem_signals[3:0] <= #1 0;
+ msr <= 0;
+ delayed_modem_signals[3:0] <= 0;
end
else begin
- msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
- msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
- msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
- delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
+ msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
+ msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
+ msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
+ delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
-end
+ end
-// Line Status Register
+ // Line Status Register
-// activation conditions
-assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
-assign lsr1 = rf_overrun; // Receiver overrun error
-assign lsr2 = rf_data_out[1]; // parity error bit
-assign lsr3 = rf_data_out[0]; // framing error bit
-assign lsr4 = rf_data_out[2]; // break error in the character
-assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
-assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
-assign lsr7 = rf_error_bit | rf_overrun;
+ // activation conditions
+ assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
+ assign lsr1 = rf_overrun; // Receiver overrun error
+ assign lsr2 = rf_data_out[1]; // parity error bit
+ assign lsr3 = rf_data_out[0]; // framing error bit
+ assign lsr4 = rf_data_out[2]; // break error in the character
+ assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
+ assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
+ assign lsr7 = rf_error_bit | rf_overrun;
-// lsr bit0 (receiver data available)
-reg lsr0_d;
+ // lsr bit0 (receiver data available)
+ reg lsr0_d;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr0_d <= #1 0;
- else lsr0_d <= #1 lsr0;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr0_d <= 0;
+ else lsr0_d <= lsr0;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr0r <= #1 0;
- else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
- lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr0r <= 0;
+ else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
+ lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
-// lsr bit 1 (receiver overrun)
-reg lsr1_d; // delayed
+ // lsr bit 1 (receiver overrun)
+ reg lsr1_d; // delayed
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr1_d <= #1 0;
- else lsr1_d <= #1 lsr1;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr1_d <= 0;
+ else lsr1_d <= lsr1;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr1r <= #1 0;
- else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr1r <= 0;
+ else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
-// lsr bit 2 (parity error)
-reg lsr2_d; // delayed
+ // lsr bit 2 (parity error)
+ reg lsr2_d; // delayed
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr2_d <= #1 0;
- else lsr2_d <= #1 lsr2;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr2_d <= 0;
+ else lsr2_d <= lsr2;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr2r <= #1 0;
- else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr2r <= 0;
+ else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
-// lsr bit 3 (framing error)
-reg lsr3_d; // delayed
+ // lsr bit 3 (framing error)
+ reg lsr3_d; // delayed
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr3_d <= #1 0;
- else lsr3_d <= #1 lsr3;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr3_d <= 0;
+ else lsr3_d <= lsr3;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr3r <= #1 0;
- else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr3r <= 0;
+ else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
-// lsr bit 4 (break indicator)
-reg lsr4_d; // delayed
+ // lsr bit 4 (break indicator)
+ reg lsr4_d; // delayed
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr4_d <= #1 0;
- else lsr4_d <= #1 lsr4;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr4_d <= 0;
+ else lsr4_d <= lsr4;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr4r <= #1 0;
- else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr4r <= 0;
+ else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
-// lsr bit 5 (transmitter fifo is empty)
-reg lsr5_d;
+ // lsr bit 5 (transmitter fifo is empty)
+ reg lsr5_d;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr5_d <= #1 1;
- else lsr5_d <= #1 lsr5;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr5_d <= 1;
+ else lsr5_d <= lsr5;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr5r <= #1 1;
- else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr5r <= 1;
+ else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
-// lsr bit 6 (transmitter empty indicator)
-reg lsr6_d;
+ // lsr bit 6 (transmitter empty indicator)
+ reg lsr6_d;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr6_d <= #1 1;
- else lsr6_d <= #1 lsr6;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr6_d <= 1;
+ else lsr6_d <= lsr6;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr6r <= #1 1;
- else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr6r <= 1;
+ else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
-// lsr bit 7 (error in fifo)
-reg lsr7_d;
+ // lsr bit 7 (error in fifo)
+ reg lsr7_d;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr7_d <= #1 0;
- else lsr7_d <= #1 lsr7;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr7_d <= 0;
+ else lsr7_d <= lsr7;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr7r <= #1 0;
- else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) lsr7r <= 0;
+ else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
-// Frequency divider
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // Frequency divider
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- dlc <= #1 0;
+ dlc <= 0;
else
- if (start_dlc | ~ (|dlc))
- dlc <= #1 dl - 1; // preset counter
- else
- dlc <= #1 dlc - 1; // decrement counter
-end
+ if (start_dlc | ~ (|dlc))
+ dlc <= dl - 1; // preset counter
+ else
+ dlc <= dlc - 1; // decrement counter
+ end
-// Enable signal generation logic
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // Enable signal generation logic
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- enable <= #1 1'b0;
+ enable <= 1'b0;
else
- if (|dl & ~(|dlc)) // dl>0 & dlc==0
- enable <= #1 1'b1;
- else
- enable <= #1 1'b0;
-end
+ if (|dl & ~(|dlc)) // dl>0 & dlc==0
+ enable <= 1'b1;
+ else
+ enable <= 1'b0;
+ end
-// Delaying THRE status for one character cycle after a character is written to an empty fifo.
-always @(lcr)
- case (lcr[3:0])
- 4'b0000 : block_value = 95; // 6 bits
- 4'b0100 : block_value = 103; // 6.5 bits
- 4'b0001, 4'b1000 : block_value = 111; // 7 bits
- 4'b1100 : block_value = 119; // 7.5 bits
- 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
- 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
- 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
- 4'b1111 : block_value = 175; // 11 bits
- endcase // case(lcr[3:0])
+ // Delaying THRE status for one character cycle after a character is written to an empty fifo.
+ always @(lcr)
+ case (lcr[3:0])
+ 4'b0000 : block_value = 95; // 6 bits
+ 4'b0100 : block_value = 103; // 6.5 bits
+ 4'b0001, 4'b1000 : block_value = 111; // 7 bits
+ 4'b1100 : block_value = 119; // 7.5 bits
+ 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
+ 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
+ 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
+ 4'b1111 : block_value = 175; // 11 bits
+ endcase // case(lcr[3:0])
-// Counting time of one character minus stop bit
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- block_cnt <= #1 8'd0;
- else
- if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
- block_cnt <= #1 block_value;
- else
- if (enable & block_cnt != 8'b0) // only work on enable times
- block_cnt <= #1 block_cnt - 1; // decrement break counter
-end // always of break condition detection
+ // Counting time of one character minus stop bit
+ always @(posedge clk or posedge wb_rst_i)
+ begin
+ if (wb_rst_i)
+ block_cnt <= 8'd0;
+ else
+ if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
+ block_cnt <= block_value;
+ else
+ if (enable & block_cnt != 8'b0) // only work on enable times
+ block_cnt <= block_cnt - 1; // decrement break counter
+ end // always of break condition detection
-// Generating THRE status enable signal
-assign thre_set_en = ~(|block_cnt);
+ // Generating THRE status enable signal
+ assign thre_set_en = ~(|block_cnt);
-//
-// INTERRUPT LOGIC
-//
+ //
+ // INTERRUPT LOGIC
+ //
-assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
-assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
-assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
-assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
-assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
+ assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
+ assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
+ assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
+ assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
+ assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
-reg rls_int_d;
-reg thre_int_d;
-reg ms_int_d;
-reg ti_int_d;
-reg rda_int_d;
+ reg rls_int_d;
+ reg thre_int_d;
+ reg ms_int_d;
+ reg ti_int_d;
+ reg rda_int_d;
-// delay lines
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rls_int_d <= #1 0;
- else rls_int_d <= #1 rls_int;
+ // delay lines
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rls_int_d <= 0;
+ else rls_int_d <= rls_int;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rda_int_d <= #1 0;
- else rda_int_d <= #1 rda_int;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rda_int_d <= 0;
+ else rda_int_d <= rda_int;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) thre_int_d <= #1 0;
- else thre_int_d <= #1 thre_int;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) thre_int_d <= 0;
+ else thre_int_d <= thre_int;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ms_int_d <= #1 0;
- else ms_int_d <= #1 ms_int;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ms_int_d <= 0;
+ else ms_int_d <= ms_int;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ti_int_d <= #1 0;
- else ti_int_d <= #1 ti_int;
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ti_int_d <= 0;
+ else ti_int_d <= ti_int;
-// rise detection signals
+ // rise detection signals
-wire rls_int_rise;
-wire thre_int_rise;
-wire ms_int_rise;
-wire ti_int_rise;
-wire rda_int_rise;
+ wire rls_int_rise;
+ wire thre_int_rise;
+ wire ms_int_rise;
+ wire ti_int_rise;
+ wire rda_int_rise;
-assign rda_int_rise = rda_int & ~rda_int_d;
-assign rls_int_rise = rls_int & ~rls_int_d;
-assign thre_int_rise = thre_int & ~thre_int_d;
-assign ms_int_rise = ms_int & ~ms_int_d;
-assign ti_int_rise = ti_int & ~ti_int_d;
+ assign rda_int_rise = rda_int & ~rda_int_d;
+ assign rls_int_rise = rls_int & ~rls_int_d;
+ assign thre_int_rise = thre_int & ~thre_int_d;
+ assign ms_int_rise = ms_int & ~ms_int_d;
+ assign ti_int_rise = ti_int & ~ti_int_d;
-// interrupt pending flags
-reg rls_int_pnd;
-reg rda_int_pnd;
-reg thre_int_pnd;
-reg ms_int_pnd;
-reg ti_int_pnd;
+ // interrupt pending flags
+ reg rls_int_pnd;
+ reg rda_int_pnd;
+ reg thre_int_pnd;
+ reg ms_int_pnd;
+ reg ti_int_pnd;
-// interrupt pending flags assignments
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rls_int_pnd <= #1 0;
- else
- rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
- rls_int_rise ? 1 : // latch condition
- rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
+ // interrupt pending flags assignments
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rls_int_pnd <= 0;
+ else
+ rls_int_pnd <= lsr_mask ? 0 : // reset condition
+ rls_int_rise ? 1 : // latch condition
+ rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rda_int_pnd <= #1 0;
- else
- rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
- rda_int_rise ? 1 : // latch condition
- rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) rda_int_pnd <= 0;
+ else
+ rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
+ rda_int_rise ? 1 : // latch condition
+ rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) thre_int_pnd <= #1 0;
- else
- thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
- thre_int_rise ? 1 :
- thre_int_pnd && ier[`UART_IE_THRE];
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) thre_int_pnd <= 0;
+ else
+ thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
+ thre_int_rise ? 1 :
+ thre_int_pnd && ier[`UART_IE_THRE];
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ms_int_pnd <= #1 0;
- else
- ms_int_pnd <= #1 msr_read ? 0 :
- ms_int_rise ? 1 :
- ms_int_pnd && ier[`UART_IE_MS];
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ms_int_pnd <= 0;
+ else
+ ms_int_pnd <= msr_read ? 0 :
+ ms_int_rise ? 1 :
+ ms_int_pnd && ier[`UART_IE_MS];
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ti_int_pnd <= #1 0;
- else
- ti_int_pnd <= #1 fifo_read ? 0 :
- ti_int_rise ? 1 :
- ti_int_pnd && ier[`UART_IE_RDA];
-// end of pending flags
+ always @(posedge clk or posedge wb_rst_i)
+ if (wb_rst_i) ti_int_pnd <= 0;
+ else
+ ti_int_pnd <= fifo_read ? 0 :
+ ti_int_rise ? 1 :
+ ti_int_pnd && ier[`UART_IE_RDA];
+ // end of pending flags
-// INT_O logic
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // INT_O logic
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- int_o <= #1 1'b0;
+ int_o <= 1'b0;
else
- int_o <= #1
- rls_int_pnd ? ~lsr_mask :
- rda_int_pnd ? 1 :
- ti_int_pnd ? ~fifo_read :
- thre_int_pnd ? !(fifo_write & iir_read) :
- ms_int_pnd ? ~msr_read :
- 0; // if no interrupt are pending
-end
+ int_o <=
+ rls_int_pnd ? ~lsr_mask :
+ rda_int_pnd ? 1 :
+ ti_int_pnd ? ~fifo_read :
+ thre_int_pnd ? !(fifo_write & iir_read) :
+ ms_int_pnd ? ~msr_read :
+ 0; // if no interrupt are pending
+ end
-// Interrupt Identification register
-always @(posedge clk or posedge wb_rst_i)
-begin
+ // Interrupt Identification register
+ always @(posedge clk or posedge wb_rst_i)
+ begin
if (wb_rst_i)
- iir <= #1 1;
+ iir <= 1;
else
- if (rls_int_pnd) // interrupt is pending
- begin
- iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
- iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
- end else // the sequence of conditions determines priority of interrupt identification
- if (rda_int)
- begin
- iir[`UART_II_II] <= #1 `UART_II_RDA;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (ti_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_TI;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (thre_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_THRE;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (ms_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_MS;
- iir[`UART_II_IP] <= #1 1'b0;
- end else // no interrupt is pending
- begin
- iir[`UART_II_II] <= #1 0;
- iir[`UART_II_IP] <= #1 1'b1;
- end
-end
+ if (rls_int_pnd) // interrupt is pending
+ begin
+ iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value
+ iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending)
+ end else // the sequence of conditions determines priority of interrupt identification
+ if (rda_int)
+ begin
+ iir[`UART_II_II] <= `UART_II_RDA;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (ti_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_TI;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (thre_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_THRE;
+ iir[`UART_II_IP] <= 1'b0;
+ end
+ else if (ms_int_pnd)
+ begin
+ iir[`UART_II_II] <= `UART_II_MS;
+ iir[`UART_II_IP] <= 1'b0;
+ end else // no interrupt is pending
+ begin
+ iir[`UART_II_II] <= 0;
+ iir[`UART_II_IP] <= 1'b1;
+ end
+ end
endmodule
/uart16550.v
0,0 → 1,353
////////////////////////////////////////////////////////////////////// |
//// //// |
//// uart_top.v //// |
//// //// |
//// //// |
//// This file is part of the "UART 16550 compatible" project //// |
//// http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Documentation related to this project: //// |
//// - http://www.opencores.org/cores/uart16550/ //// |
//// //// |
//// Projects compatibility: //// |
//// - WISHBONE //// |
//// RS232 Protocol //// |
//// 16550D uart (mostly supported) //// |
//// //// |
//// Overview (main Features): //// |
//// UART core top level. //// |
//// //// |
//// Known problems (limits): //// |
//// Note that transmitter and receiver instances are inside //// |
//// the uart_regs.v file. //// |
//// //// |
//// To Do: //// |
//// Nothing so far. //// |
//// //// |
//// Author(s): //// |
//// - gorban@opencores.org //// |
//// - Jacob Gorban //// |
//// - Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// Created: 2001/05/12 //// |
//// Last Updated: 2001/05/17 //// |
//// (See log for the revision history) //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000, 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.17 2001/12/19 08:40:03 mohor |
// Warnings fixed (unused signals removed). |
// |
// Revision 1.16 2001/12/06 14:51:04 gorban |
// Bug in LSR[0] is fixed. |
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
// |
// Revision 1.15 2001/12/03 21:44:29 gorban |
// Updated specification documentation. |
// Added full 32-bit data bus interface, now as default. |
// Address is 5-bit wide in 32-bit data bus mode. |
// Added wb_sel_i input to the core. It's used in the 32-bit mode. |
// Added debug interface with two 32-bit read-only registers in 32-bit mode. |
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
// My small test bench is modified to work with 32-bit mode. |
// |
// Revision 1.14 2001/11/07 17:51:52 gorban |
// Heavily rewritten interrupt and LSR subsystems. |
// Many bugs hopefully squashed. |
// |
// Revision 1.13 2001/10/20 09:58:40 gorban |
// Small synopsis fixes |
// |
// Revision 1.12 2001/08/25 15:46:19 gorban |
// Modified port names again |
// |
// Revision 1.11 2001/08/24 21:01:12 mohor |
// Things connected to parity changed. |
// Clock devider changed. |
// |
// Revision 1.10 2001/08/23 16:05:05 mohor |
// Stop bit bug fixed. |
// Parity bug fixed. |
// WISHBONE read cycle bug fixed, |
// OE indicator (Overrun Error) bug fixed. |
// PE indicator (Parity Error) bug fixed. |
// Register read bug fixed. |
// |
// Revision 1.4 2001/05/31 20:08:01 gorban |
// FIFO changes and other corrections. |
// |
// Revision 1.3 2001/05/21 19:12:02 gorban |
// Corrected some Linter messages. |
// |
// Revision 1.2 2001/05/17 18:34:18 gorban |
// First 'stable' release. Should be sythesizable now. Also added new header. |
// |
// Revision 1.0 2001-05-17 21:27:12+02 jacob |
// Initial revision |
// |
// |
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
`include "uart_defines.v" |
|
//module uart_top ( |
module uart16550( // renamed by Julius |
wb_clk_i, |
|
// Wishbone signals |
wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_dat_o, |
`ifndef DATA_BUS_WIDTH_8 |
wb_sel_i, |
`endif |
wb_stb_i, wb_cyc_i, wb_ack_o, |
int_o, // interrupt request |
|
// UART signals |
// serial input/output |
stx_pad_o, srx_pad_i, |
|
// modem signals |
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, |
dcd_pad_i |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
, baud_o |
`endif |
); |
|
parameter uart_data_width = `UART_DATA_WIDTH; |
parameter uart_addr_width = `UART_ADDR_WIDTH; |
|
input wb_clk_i; |
|
// WISHBONE interface |
input wb_rst_i; |
input [uart_addr_width-1:0] wb_adr_i; |
input [uart_data_width-1:0] wb_dat_i; |
output [uart_data_width-1:0] wb_dat_o; |
input wb_we_i; |
input wb_stb_i; |
input wb_cyc_i; |
`ifndef DATA_BUS_WIDTH_8 |
input [3:0] wb_sel_i; |
`endif |
output wb_ack_o; |
output int_o; |
|
// UART signals |
input srx_pad_i; |
output stx_pad_o; |
output rts_pad_o; |
input cts_pad_i; |
output dtr_pad_o; |
input dsr_pad_i; |
input ri_pad_i; |
input dcd_pad_i; |
|
// optional baudrate output |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
output baud_o; |
`endif |
|
|
wire stx_pad_o; |
wire rts_pad_o; |
wire dtr_pad_o; |
|
wire [uart_addr_width-1:0] wb_adr_i; |
wire [uart_data_width-1:0] wb_dat_i; |
wire [uart_data_width-1:0] wb_dat_o; |
|
wire [7:0] wb_dat8_i; // 8-bit internal data input |
wire [7:0] wb_dat8_o; // 8-bit internal data output |
wire [31:0] wb_dat32_o; // debug interface 32-bit output |
wire [3:0] wb_sel_i; // WISHBONE select signal |
wire [uart_addr_width-1:0] wb_adr_int; |
wire we_o; // Write enable for registers |
wire re_o; // Read enable for registers |
// |
// MODULE INSTANCES |
// |
|
`ifdef DATA_BUS_WIDTH_8 |
`else |
// debug interface wires |
wire [3:0] ier; |
wire [3:0] iir; |
wire [1:0] fcr; |
wire [4:0] mcr; |
wire [7:0] lcr; |
wire [7:0] msr; |
wire [7:0] lsr; |
wire [`UART_FIFO_COUNTER_W-1:0] rf_count; |
wire [`UART_FIFO_COUNTER_W-1:0] tf_count; |
wire [2:0] tstate; |
wire [3:0] rstate; |
`endif |
|
`ifdef DATA_BUS_WIDTH_8 |
//// WISHBONE interface module |
uart_wb wb_interface |
( |
.clk( wb_clk_i ), |
.wb_rst_i( wb_rst_i ), |
.wb_dat_i(wb_dat_i), |
.wb_dat_o(wb_dat_o), |
.wb_dat8_i(wb_dat8_i), |
.wb_dat8_o(wb_dat8_o), |
.wb_dat32_o(32'b0), |
.wb_sel_i(4'b0), |
.wb_we_i( wb_we_i ), |
.wb_stb_i( wb_stb_i ), |
.wb_cyc_i( wb_cyc_i ), |
.wb_ack_o( wb_ack_o ), |
.wb_adr_i(wb_adr_i), |
.wb_adr_int(wb_adr_int), |
.we_o( we_o ), |
.re_o(re_o) |
); |
`else |
uart_wb wb_interface |
( |
.clk( wb_clk_i ), |
.wb_rst_i( wb_rst_i ), |
.wb_dat_i(wb_dat_i), |
.wb_dat_o(wb_dat_o), |
.wb_dat8_i(wb_dat8_i), |
.wb_dat8_o(wb_dat8_o), |
.wb_sel_i(wb_sel_i), |
.wb_dat32_o(wb_dat32_o), |
.wb_we_i( wb_we_i ), |
.wb_stb_i( wb_stb_i ), |
.wb_cyc_i( wb_cyc_i ), |
.wb_ack_o( wb_ack_o ), |
.wb_adr_i(wb_adr_i), |
.wb_adr_int(wb_adr_int), |
.we_o( we_o ), |
.re_o(re_o) |
); |
`endif |
|
// Registers |
uart_regs regs |
( |
.clk( wb_clk_i ), |
.wb_rst_i( wb_rst_i ), |
.wb_addr_i( wb_adr_int ), |
.wb_dat_i( wb_dat8_i ), |
.wb_dat_o( wb_dat8_o ), |
.wb_we_i( we_o ), |
.wb_re_i(re_o), |
.modem_inputs( {cts_pad_i, dsr_pad_i, |
ri_pad_i, dcd_pad_i} ), |
.stx_pad_o( stx_pad_o ), |
.srx_pad_i( srx_pad_i ), |
`ifdef DATA_BUS_WIDTH_8 |
`else |
// debug interface signals enabled |
.ier(ier), |
.iir(iir), |
.fcr(fcr), |
.mcr(mcr), |
.lcr(lcr), |
.msr(msr), |
.lsr(lsr), |
.rf_count(rf_count), |
.tf_count(tf_count), |
.tstate(tstate), |
.rstate(rstate), |
`endif |
.rts_pad_o( rts_pad_o ), |
.dtr_pad_o( dtr_pad_o ), |
.int_o( int_o ) |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
, .baud_o(baud_o) |
`endif |
|
); |
|
`ifdef DATA_BUS_WIDTH_8 |
`else |
uart_debug_if dbg |
( |
// Outputs |
.wb_dat32_o (wb_dat32_o[31:0]), |
// Inputs |
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]), |
.ier (ier[3:0]), |
.iir (iir[3:0]), |
.fcr (fcr[1:0]), |
.mcr (mcr[4:0]), |
.lcr (lcr[7:0]), |
.msr (msr[7:0]), |
.lsr (lsr[7:0]), |
.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]), |
.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]), |
.tstate (tstate[2:0]), |
.rstate (rstate[3:0])); |
`endif |
|
/* |
initial |
begin |
`ifdef DATA_BUS_WIDTH_8 |
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n"); |
`else |
$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n"); |
`endif |
`ifdef UART_HAS_BAUDRATE_OUTPUT |
$display("(%m) UART INFO: Has baudrate output\n"); |
`else |
$display("(%m) UART INFO: Doesn't have baudrate output\n"); |
`endif |
end |
*/ |
endmodule |
|
|
uart16550.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: raminfr.v
===================================================================
--- raminfr.v (.../components/uart16550) (revision 55)
+++ raminfr.v (.../uart16550) (revision 360)
@@ -61,10 +61,7 @@
//
// CVS Revision History
//
-// $Log: raminfr.v,v $
-// Revision 1.2 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
+// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
@@ -83,7 +80,6 @@
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
-`include "uart_defines.v"
module raminfr
(clk, we, a, dpra, di, dpo);
@@ -99,12 +95,8 @@
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
-`ifdef SYNC_RAM
- reg [data_width-1:0] dpo;
-`else
- wire [data_width-1:0] dpo;
-`endif
-
+
+wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
@@ -113,13 +105,7 @@
if (we)
ram[a] <= di;
end
-
-`ifdef SYNC_RAM
- always @(negedge clk)
- dpo = ram[dpra];
-`else
- assign dpo = ram[dpra];
-`endif
-
+// assign spo = ram[a];
+ assign dpo = ram[dpra];
endmodule
/uart_debug_if.v
53,10 → 53,7
// |
// CVS Revision History |
// |
// $Log: uart_debug_if.v,v $ |
// Revision 1.5 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
/uart_receiver.v
62,10 → 62,7
// |
// CVS Revision History |
// |
// $Log: uart_receiver.v,v $ |
// Revision 1.31 2004/06/18 14:46:15 tadejm |
// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.29 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
199,287 → 196,287
`include "uart_defines.v" |
|
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, |
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); |
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); |
|
input clk; |
input wb_rst_i; |
input [7:0] lcr; |
input rf_pop; |
input srx_pad_i; |
input enable; |
input rx_reset; |
input lsr_mask; |
input clk; |
input wb_rst_i; |
input [7:0] lcr; |
input rf_pop; |
input srx_pad_i; |
input enable; |
input rx_reset; |
input lsr_mask; |
|
output [9:0] counter_t; |
output [`UART_FIFO_COUNTER_W-1:0] rf_count; |
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
output rf_overrun; |
output rf_error_bit; |
output [3:0] rstate; |
output rf_push_pulse; |
output [9:0] counter_t; |
output [`UART_FIFO_COUNTER_W-1:0] rf_count; |
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
output rf_overrun; |
output rf_error_bit; |
output [3:0] rstate; |
output rf_push_pulse; |
|
reg [3:0] rstate; |
reg [3:0] rcounter16; |
reg [2:0] rbit_counter; |
reg [7:0] rshift; // receiver shift register |
reg rparity; // received parity |
reg rparity_error; |
reg rframing_error; // framing error flag |
reg rbit_in; |
reg rparity_xor; |
reg [7:0] counter_b; // counts the 0 (low) signals |
reg rf_push_q; |
reg [3:0] rstate; |
reg [3:0] rcounter16; |
reg [2:0] rbit_counter; |
reg [7:0] rshift; // receiver shift register |
reg rparity; // received parity |
reg rparity_error; |
reg rframing_error; // framing error flag |
reg rbit_in; |
reg rparity_xor; |
reg [7:0] counter_b; // counts the 0 (low) signals |
reg rf_push_q; |
|
// RX FIFO signals |
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; |
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
wire rf_push_pulse; |
reg rf_push; |
wire rf_pop; |
wire rf_overrun; |
wire [`UART_FIFO_COUNTER_W-1:0] rf_count; |
wire rf_error_bit; // an error (parity or framing) is inside the fifo |
wire break_error = (counter_b == 0); |
// RX FIFO signals |
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; |
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; |
wire rf_push_pulse; |
reg rf_push; |
wire rf_pop; |
wire rf_overrun; |
wire [`UART_FIFO_COUNTER_W-1:0] rf_count; |
wire rf_error_bit; // an error (parity or framing) is inside the fifo |
wire break_error = (counter_b == 0); |
|
// RX FIFO instance |
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( |
.clk( clk ), |
.wb_rst_i( wb_rst_i ), |
.data_in( rf_data_in ), |
.data_out( rf_data_out ), |
.push( rf_push_pulse ), |
.pop( rf_pop ), |
.overrun( rf_overrun ), |
.count( rf_count ), |
.error_bit( rf_error_bit ), |
.fifo_reset( rx_reset ), |
.reset_status(lsr_mask) |
); |
// RX FIFO instance |
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( |
.clk( clk ), |
.wb_rst_i( wb_rst_i ), |
.data_in( rf_data_in ), |
.data_out( rf_data_out ), |
.push( rf_push_pulse ), |
.pop( rf_pop ), |
.overrun( rf_overrun ), |
.count( rf_count ), |
.error_bit( rf_error_bit ), |
.fifo_reset( rx_reset ), |
.reset_status(lsr_mask) |
); |
|
wire rcounter16_eq_7 = (rcounter16 == 4'd7); |
wire rcounter16_eq_0 = (rcounter16 == 4'd0); |
wire rcounter16_eq_1 = (rcounter16 == 4'd1); |
wire rcounter16_eq_7 = (rcounter16 == 4'd7); |
wire rcounter16_eq_0 = (rcounter16 == 4'd0); |
wire rcounter16_eq_1 = (rcounter16 == 4'd1); |
|
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; |
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; |
|
parameter sr_idle = 4'd0; |
parameter sr_rec_start = 4'd1; |
parameter sr_rec_bit = 4'd2; |
parameter sr_rec_parity = 4'd3; |
parameter sr_rec_stop = 4'd4; |
parameter sr_check_parity = 4'd5; |
parameter sr_rec_prepare = 4'd6; |
parameter sr_end_bit = 4'd7; |
parameter sr_ca_lc_parity = 4'd8; |
parameter sr_wait1 = 4'd9; |
parameter sr_push = 4'd10; |
parameter sr_idle = 4'd0; |
parameter sr_rec_start = 4'd1; |
parameter sr_rec_bit = 4'd2; |
parameter sr_rec_parity = 4'd3; |
parameter sr_rec_stop = 4'd4; |
parameter sr_check_parity = 4'd5; |
parameter sr_rec_prepare = 4'd6; |
parameter sr_end_bit = 4'd7; |
parameter sr_ca_lc_parity = 4'd8; |
parameter sr_wait1 = 4'd9; |
parameter sr_push = 4'd10; |
|
|
always @(posedge clk or posedge wb_rst_i) |
begin |
if (wb_rst_i) |
begin |
rstate <= #1 sr_idle; |
rbit_in <= #1 1'b0; |
rcounter16 <= #1 0; |
rbit_counter <= #1 0; |
rparity_xor <= #1 1'b0; |
rframing_error <= #1 1'b0; |
rparity_error <= #1 1'b0; |
rparity <= #1 1'b0; |
rshift <= #1 0; |
rf_push <= #1 1'b0; |
rf_data_in <= #1 0; |
end |
else |
if (enable) |
begin |
case (rstate) |
sr_idle : begin |
rf_push <= #1 1'b0; |
rf_data_in <= #1 0; |
rcounter16 <= #1 4'b1110; |
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) |
always @(posedge clk or posedge wb_rst_i) |
begin |
if (wb_rst_i) |
begin |
rstate <= sr_idle; |
rbit_in <= 1'b0; |
rcounter16 <= 0; |
rbit_counter <= 0; |
rparity_xor <= 1'b0; |
rframing_error <= 1'b0; |
rparity_error <= 1'b0; |
rparity <= 1'b0; |
rshift <= 0; |
rf_push <= 1'b0; |
rf_data_in <= 0; |
end |
else |
if (enable) |
begin |
case (rstate) |
sr_idle : begin |
rf_push <= 1'b0; |
rf_data_in <= 0; |
rcounter16 <= 4'b1110; |
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) |
begin |
rstate <= sr_rec_start; |
end |
end |
sr_rec_start : begin |
rf_push <= 1'b0; |
if (rcounter16_eq_7) // check the pulse |
if (srx_pad_i==1'b1) // no start bit |
rstate <= sr_idle; |
else // start bit detected |
rstate <= sr_rec_prepare; |
rcounter16 <= rcounter16_minus_1; |
end |
sr_rec_prepare:begin |
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
2'b00 : rbit_counter <= 3'b100; |
2'b01 : rbit_counter <= 3'b101; |
2'b10 : rbit_counter <= 3'b110; |
2'b11 : rbit_counter <= 3'b111; |
endcase |
if (rcounter16_eq_0) |
begin |
rstate <= sr_rec_bit; |
rcounter16 <= 4'b1110; |
rshift <= 0; |
end |
else |
rstate <= sr_rec_prepare; |
rcounter16 <= rcounter16_minus_1; |
end |
sr_rec_bit : begin |
if (rcounter16_eq_0) |
rstate <= sr_end_bit; |
if (rcounter16_eq_7) // read the bit |
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]}; |
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]}; |
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]}; |
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]}; |
endcase |
rcounter16 <= rcounter16_minus_1; |
end |
sr_end_bit : begin |
if (rbit_counter==3'b0) // no more bits in word |
if (lcr[`UART_LC_PE]) // choose state based on parity |
rstate <= sr_rec_parity; |
else |
begin |
rstate <= #1 sr_rec_start; |
rstate <= sr_rec_stop; |
rparity_error <= 1'b0; // no parity - no error :) |
end |
end |
sr_rec_start : begin |
rf_push <= #1 1'b0; |
if (rcounter16_eq_7) // check the pulse |
if (srx_pad_i==1'b1) // no start bit |
rstate <= #1 sr_idle; |
else // start bit detected |
rstate <= #1 sr_rec_prepare; |
rcounter16 <= #1 rcounter16_minus_1; |
end |
sr_rec_prepare:begin |
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
2'b00 : rbit_counter <= #1 3'b100; |
2'b01 : rbit_counter <= #1 3'b101; |
2'b10 : rbit_counter <= #1 3'b110; |
2'b11 : rbit_counter <= #1 3'b111; |
endcase |
if (rcounter16_eq_0) |
begin |
rstate <= #1 sr_rec_bit; |
rcounter16 <= #1 4'b1110; |
rshift <= #1 0; |
end |
else |
rstate <= #1 sr_rec_prepare; |
rcounter16 <= #1 rcounter16_minus_1; |
end |
sr_rec_bit : begin |
if (rcounter16_eq_0) |
rstate <= #1 sr_end_bit; |
if (rcounter16_eq_7) // read the bit |
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]}; |
2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]}; |
2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]}; |
2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]}; |
endcase |
rcounter16 <= #1 rcounter16_minus_1; |
end |
sr_end_bit : begin |
if (rbit_counter==3'b0) // no more bits in word |
if (lcr[`UART_LC_PE]) // choose state based on parity |
rstate <= #1 sr_rec_parity; |
else |
begin |
rstate <= #1 sr_rec_stop; |
rparity_error <= #1 1'b0; // no parity - no error :) |
end |
else // else we have more bits to read |
begin |
rstate <= #1 sr_rec_bit; |
rbit_counter <= #1 rbit_counter - 1'b1; |
end |
rcounter16 <= #1 4'b1110; |
end |
sr_rec_parity: begin |
if (rcounter16_eq_7) // read the parity |
begin |
rparity <= #1 srx_pad_i; |
rstate <= #1 sr_ca_lc_parity; |
end |
rcounter16 <= #1 rcounter16_minus_1; |
end |
sr_ca_lc_parity : begin // rcounter equals 6 |
rcounter16 <= #1 rcounter16_minus_1; |
rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data |
rstate <= #1 sr_check_parity; |
end |
sr_check_parity: begin // rcounter equals 5 |
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) |
2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1 |
2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1 |
2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd |
2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0 |
endcase |
rcounter16 <= #1 rcounter16_minus_1; |
rstate <= #1 sr_wait1; |
end |
sr_wait1 : if (rcounter16_eq_0) |
begin |
rstate <= #1 sr_rec_stop; |
rcounter16 <= #1 4'b1110; |
end |
else |
rcounter16 <= #1 rcounter16_minus_1; |
sr_rec_stop : begin |
if (rcounter16_eq_7) // read the parity |
begin |
rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit) |
rstate <= #1 sr_push; |
end |
rcounter16 <= #1 rcounter16_minus_1; |
end |
sr_push : begin |
/////////////////////////////////////// |
// $display($time, ": received: %b", rf_data_in); |
if(srx_pad_i | break_error) |
begin |
if(break_error) |
rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO |
else |
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; |
rf_push <= #1 1'b1; |
rstate <= #1 sr_idle; |
end |
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i |
begin |
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; |
rf_push <= #1 1'b1; |
rcounter16 <= #1 4'b1110; |
rstate <= #1 sr_rec_start; |
end |
|
end |
default : rstate <= #1 sr_idle; |
endcase |
end // if (enable) |
end // always of receiver |
else // else we have more bits to read |
begin |
rstate <= sr_rec_bit; |
rbit_counter <= rbit_counter - 1'b1; |
end |
rcounter16 <= 4'b1110; |
end |
sr_rec_parity: begin |
if (rcounter16_eq_7) // read the parity |
begin |
rparity <= srx_pad_i; |
rstate <= sr_ca_lc_parity; |
end |
rcounter16 <= rcounter16_minus_1; |
end |
sr_ca_lc_parity : begin // rcounter equals 6 |
rcounter16 <= rcounter16_minus_1; |
rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data |
rstate <= sr_check_parity; |
end |
sr_check_parity: begin // rcounter equals 5 |
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) |
2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1 |
2'b01: rparity_error <= ~rparity; // parity should sticked to 1 |
2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd |
2'b11: rparity_error <= rparity; // parity should be sticked to 0 |
endcase |
rcounter16 <= rcounter16_minus_1; |
rstate <= sr_wait1; |
end |
sr_wait1 : if (rcounter16_eq_0) |
begin |
rstate <= sr_rec_stop; |
rcounter16 <= 4'b1110; |
end |
else |
rcounter16 <= rcounter16_minus_1; |
sr_rec_stop : begin |
if (rcounter16_eq_7) // read the parity |
begin |
rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit) |
rstate <= sr_push; |
end |
rcounter16 <= rcounter16_minus_1; |
end |
sr_push : begin |
/////////////////////////////////////// |
// $display($time, ": received: %b", rf_data_in); |
if(srx_pad_i | break_error) |
begin |
if(break_error) |
rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO |
else |
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; |
rf_push <= 1'b1; |
rstate <= sr_idle; |
end |
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i |
begin |
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; |
rf_push <= 1'b1; |
rcounter16 <= 4'b1110; |
rstate <= sr_rec_start; |
end |
|
end |
default : rstate <= sr_idle; |
endcase |
end // if (enable) |
end // always of receiver |
|
always @ (posedge clk or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
rf_push_q <= 0; |
else |
rf_push_q <= #1 rf_push; |
end |
always @ (posedge clk or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
rf_push_q <= 0; |
else |
rf_push_q <= rf_push; |
end |
|
assign rf_push_pulse = rf_push & ~rf_push_q; |
assign rf_push_pulse = rf_push & ~rf_push_q; |
|
|
// |
// Break condition detection. |
// Works in conjuction with the receiver state machine |
|
// |
// Break condition detection. |
// Works in conjuction with the receiver state machine |
|
reg [9:0] toc_value; // value to be set to timeout counter |
reg [9:0] toc_value; // value to be set to timeout counter |
|
always @(lcr) |
case (lcr[3:0]) |
4'b0000 : toc_value = 447; // 7 bits |
4'b0100 : toc_value = 479; // 7.5 bits |
4'b0001, 4'b1000 : toc_value = 511; // 8 bits |
4'b1100 : toc_value = 543; // 8.5 bits |
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits |
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits |
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits |
4'b1111 : toc_value = 767; // 12 bits |
endcase // case(lcr[3:0]) |
always @(lcr) |
case (lcr[3:0]) |
4'b0000: toc_value = 447; // 7 bits |
4'b0100: toc_value = 479; // 7.5 bits |
4'b0001, 4'b1000 : toc_value = 511; // 8 bits |
4'b1100: toc_value = 543; // 8.5 bits |
4'b0010, 4'b0101, 4'b1001: toc_value = 575; // 9 bits |
4'b0011, 4'b0110, 4'b1010, 4'b1101: toc_value = 639; // 10 bits |
4'b0111, 4'b1011, 4'b1110: toc_value = 703; // 11 bits |
4'b1111: toc_value = 767; // 12 bits |
endcase // case(lcr[3:0]) |
|
wire [7:0] brc_value; // value to be set to break counter |
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times |
wire [7:0] brc_value; // value to be set to break counter |
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times |
|
always @(posedge clk or posedge wb_rst_i) |
begin |
always @(posedge clk or posedge wb_rst_i) |
begin |
if (wb_rst_i) |
counter_b <= #1 8'd159; |
counter_b <= 8'd159; |
else |
if (srx_pad_i) |
counter_b <= #1 brc_value; // character time length - 1 |
else |
if(enable & counter_b != 8'b0) // only work on enable times break not reached. |
counter_b <= #1 counter_b - 1; // decrement break counter |
end // always of break condition detection |
if (srx_pad_i) |
counter_b <= brc_value; // character time length - 1 |
else |
if(enable & counter_b != 8'b0) // only work on enable times break not reached. |
counter_b <= counter_b - 1; // decrement break counter |
end // always of break condition detection |
|
/// |
/// Timeout condition detection |
reg [9:0] counter_t; // counts the timeout condition clocks |
/// |
/// Timeout condition detection |
reg [9:0] counter_t; // counts the timeout condition clocks |
|
always @(posedge clk or posedge wb_rst_i) |
begin |
always @(posedge clk or posedge wb_rst_i) |
begin |
if (wb_rst_i) |
counter_t <= #1 10'd639; // 10 bits for the default 8N1 |
counter_t <= 10'd639; // 10 bits for the default 8N1 |
else |
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level |
counter_t <= #1 toc_value; |
else |
if (enable && counter_t != 10'b0) // we don't want to underflow |
counter_t <= #1 counter_t - 1; |
end |
|
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level |
counter_t <= toc_value; |
else |
if (enable && counter_t != 10'b0) // we don't want to underflow |
counter_t <= counter_t - 1; |
end |
|
endmodule |
/uart_rfifo.v
59,10 → 59,7
// |
// CVS Revision History |
// |
// $Log: uart_rfifo.v,v $ |
// Revision 1.4 2003/07/11 18:20:26 gorban |
// added clearing the receiver fifo statuses on resets |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/06/11 16:37:47 gorban |
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. |
// |
210,47 → 207,47
begin |
if (wb_rst_i) |
begin |
top <= #1 0; |
bottom <= #1 1'b0; |
count <= #1 0; |
fifo[0] <= #1 0; |
fifo[1] <= #1 0; |
fifo[2] <= #1 0; |
fifo[3] <= #1 0; |
fifo[4] <= #1 0; |
fifo[5] <= #1 0; |
fifo[6] <= #1 0; |
fifo[7] <= #1 0; |
fifo[8] <= #1 0; |
fifo[9] <= #1 0; |
fifo[10] <= #1 0; |
fifo[11] <= #1 0; |
fifo[12] <= #1 0; |
fifo[13] <= #1 0; |
fifo[14] <= #1 0; |
fifo[15] <= #1 0; |
top <= 0; |
bottom <= 1'b0; |
count <= 0; |
fifo[0] <= 0; |
fifo[1] <= 0; |
fifo[2] <= 0; |
fifo[3] <= 0; |
fifo[4] <= 0; |
fifo[5] <= 0; |
fifo[6] <= 0; |
fifo[7] <= 0; |
fifo[8] <= 0; |
fifo[9] <= 0; |
fifo[10] <= 0; |
fifo[11] <= 0; |
fifo[12] <= 0; |
fifo[13] <= 0; |
fifo[14] <= 0; |
fifo[15] <= 0; |
end |
else |
if (fifo_reset) begin |
top <= #1 0; |
bottom <= #1 1'b0; |
count <= #1 0; |
fifo[0] <= #1 0; |
fifo[1] <= #1 0; |
fifo[2] <= #1 0; |
fifo[3] <= #1 0; |
fifo[4] <= #1 0; |
fifo[5] <= #1 0; |
fifo[6] <= #1 0; |
fifo[7] <= #1 0; |
fifo[8] <= #1 0; |
fifo[9] <= #1 0; |
fifo[10] <= #1 0; |
fifo[11] <= #1 0; |
fifo[12] <= #1 0; |
fifo[13] <= #1 0; |
fifo[14] <= #1 0; |
fifo[15] <= #1 0; |
top <= 0; |
bottom <= 1'b0; |
count <= 0; |
fifo[0] <= 0; |
fifo[1] <= 0; |
fifo[2] <= 0; |
fifo[3] <= 0; |
fifo[4] <= 0; |
fifo[5] <= 0; |
fifo[6] <= 0; |
fifo[7] <= 0; |
fifo[8] <= 0; |
fifo[9] <= 0; |
fifo[10] <= 0; |
fifo[11] <= 0; |
fifo[12] <= 0; |
fifo[13] <= 0; |
fifo[14] <= 0; |
fifo[15] <= 0; |
end |
else |
begin |
257,20 → 254,20
case ({push, pop}) |
2'b10 : if (count<fifo_depth) // overrun condition |
begin |
top <= #1 top_plus_1; |
fifo[top] <= #1 data_in[2:0]; |
count <= #1 count + 1'b1; |
top <= top_plus_1; |
fifo[top] <= data_in[2:0]; |
count <= count + 1'b1; |
end |
2'b01 : if(count>0) |
begin |
fifo[bottom] <= #1 0; |
bottom <= #1 bottom + 1'b1; |
count <= #1 count - 1'b1; |
fifo[bottom] <= 0; |
bottom <= bottom + 1'b1; |
count <= count - 1'b1; |
end |
2'b11 : begin |
bottom <= #1 bottom + 1'b1; |
top <= #1 top_plus_1; |
fifo[top] <= #1 data_in[2:0]; |
bottom <= bottom + 1'b1; |
top <= top_plus_1; |
fifo[top] <= data_in[2:0]; |
end |
default: ; |
endcase |
280,13 → 277,13
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO |
begin |
if (wb_rst_i) |
overrun <= #1 1'b0; |
overrun <= 1'b0; |
else |
if(fifo_reset | reset_status) |
overrun <= #1 1'b0; |
overrun <= 1'b0; |
else |
if(push & ~pop & (count==fifo_depth)) |
overrun <= #1 1'b1; |
overrun <= 1'b1; |
end // always |
|
|
/uart_tfifo.v
59,10 → 59,7
// |
// CVS Revision History |
// |
// $Log: uart_tfifo.v,v $ |
// Revision 1.2 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
199,15 → 196,15
begin |
if (wb_rst_i) |
begin |
top <= #1 0; |
bottom <= #1 1'b0; |
count <= #1 0; |
top <= 0; |
bottom <= 1'b0; |
count <= 0; |
end |
else |
if (fifo_reset) begin |
top <= #1 0; |
bottom <= #1 1'b0; |
count <= #1 0; |
top <= 0; |
bottom <= 1'b0; |
count <= 0; |
end |
else |
begin |
214,17 → 211,17
case ({push, pop}) |
2'b10 : if (count<fifo_depth) // overrun condition |
begin |
top <= #1 top_plus_1; |
count <= #1 count + 1'b1; |
top <= top_plus_1; |
count <= count + 1'b1; |
end |
2'b01 : if(count>0) |
begin |
bottom <= #1 bottom + 1'b1; |
count <= #1 count - 1'b1; |
bottom <= bottom + 1'b1; |
count <= count - 1'b1; |
end |
2'b11 : begin |
bottom <= #1 bottom + 1'b1; |
top <= #1 top_plus_1; |
bottom <= bottom + 1'b1; |
top <= top_plus_1; |
end |
default: ; |
endcase |
234,13 → 231,13
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO |
begin |
if (wb_rst_i) |
overrun <= #1 1'b0; |
overrun <= 1'b0; |
else |
if(fifo_reset | reset_status) |
overrun <= #1 1'b0; |
overrun <= 1'b0; |
else |
if(push & (count==fifo_depth)) |
overrun <= #1 1'b1; |
overrun <= 1'b1; |
end // always |
|
endmodule |
/uart_wb.v
63,10 → 63,7
// |
// CVS Revision History |
// |
// $Log: uart_wb.v,v $ |
// Revision 1.17 2004/05/21 12:35:15 tadejm |
// Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
197,30 → 194,30
reg [1:0] wbstate; |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) begin |
wb_ack_o <= #1 1'b0; |
wbstate <= #1 0; |
wre <= #1 1'b1; |
wb_ack_o <= 1'b0; |
wbstate <= 0; |
wre <= 1'b1; |
end else |
case (wbstate) |
0: begin |
if (wb_stb_is & wb_cyc_is) begin |
wre <= #1 0; |
wbstate <= #1 1; |
wb_ack_o <= #1 1; |
wre <= 0; |
wbstate <= 1; |
wb_ack_o <= 1; |
end else begin |
wre <= #1 1; |
wb_ack_o <= #1 0; |
wre <= 1; |
wb_ack_o <= 0; |
end |
end |
1: begin |
wb_ack_o <= #1 0; |
wbstate <= #1 2; |
wre <= #1 0; |
wb_ack_o <= 0; |
wbstate <= 2; |
wre <= 0; |
end |
2,3: begin |
wb_ack_o <= #1 0; |
wbstate <= #1 0; |
wre <= #1 0; |
wb_ack_o <= 0; |
wbstate <= 0; |
wre <= 0; |
end |
endcase |
|
230,27 → 227,27
// Sample input signals |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) begin |
wb_adr_is <= #1 0; |
wb_we_is <= #1 0; |
wb_cyc_is <= #1 0; |
wb_stb_is <= #1 0; |
wb_dat_is <= #1 0; |
wb_sel_is <= #1 0; |
wb_adr_is <= 0; |
wb_we_is <= 0; |
wb_cyc_is <= 0; |
wb_stb_is <= 0; |
wb_dat_is <= 0; |
wb_sel_is <= 0; |
end else begin |
wb_adr_is <= #1 wb_adr_i; |
wb_we_is <= #1 wb_we_i; |
wb_cyc_is <= #1 wb_cyc_i; |
wb_stb_is <= #1 wb_stb_i; |
wb_dat_is <= #1 wb_dat_i; |
wb_sel_is <= #1 wb_sel_i; |
wb_adr_is <= wb_adr_i; |
wb_we_is <= wb_we_i; |
wb_cyc_is <= wb_cyc_i; |
wb_stb_is <= wb_stb_i; |
wb_dat_is <= wb_dat_i; |
wb_sel_is <= wb_sel_i; |
end |
|
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) |
wb_dat_o <= #1 0; |
wb_dat_o <= 0; |
else |
wb_dat_o <= #1 wb_dat8_o; |
wb_dat_o <= wb_dat8_o; |
|
always @(wb_dat_is) |
wb_dat8_i = wb_dat_is; |
261,15 → 258,15
// put output to the correct byte in 32 bits using select line |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) |
wb_dat_o <= #1 0; |
wb_dat_o <= 0; |
else if (re_o) |
case (wb_sel_is) |
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o}; |
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0}; |
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0}; |
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0}; |
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output |
default: wb_dat_o <= #1 0; |
4'b0001: wb_dat_o <= {24'b0, wb_dat8_o}; |
4'b0010: wb_dat_o <= {16'b0, wb_dat8_o, 8'b0}; |
4'b0100: wb_dat_o <= {8'b0, wb_dat8_o, 16'b0}; |
4'b1000: wb_dat_o <= {wb_dat8_o, 24'b0}; |
4'b1111: wb_dat_o <= wb_dat32_o; // debug interface output |
default: wb_dat_o <= 0; |
endcase // case(wb_sel_i) |
|
reg [1:0] wb_adr_int_lsb; |
/uart_transmitter.v
62,10 → 62,7
// |
// CVS Revision History |
// |
// $Log: uart_transmitter.v,v $ |
// Revision 1.19 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
201,25 → 198,8
.reset_status(lsr_mask) |
); |
|
`ifdef UART_LOG_TX |
integer file_handler; |
// TRANSMITTER FINAL STATE MACHINE |
|
initial |
begin |
file_handler = $fopen("uart_tx.txt", "w"); |
end |
|
always @(negedge tf_push) |
begin |
$fwrite(file_handler, "%s", tf_data_out); |
`ifdef UART16550_SIM_OUTPUT |
$display("UART: %s", tf_data_out); |
`endif |
end |
`endif |
|
// TRANSMITTER FINAL STATE MACHINE |
|
parameter s_idle = 3'd0; |
parameter s_send_start = 3'd1; |
parameter s_send_byte = 3'd2; |
231,14 → 211,14
begin |
if (wb_rst_i) |
begin |
tstate <= #1 s_idle; |
stx_o_tmp <= #1 1'b1; |
counter <= #1 5'b0; |
shift_out <= #1 7'b0; |
bit_out <= #1 1'b0; |
parity_xor <= #1 1'b0; |
tf_pop <= #1 1'b0; |
bit_counter <= #1 3'b0; |
tstate <= s_idle; |
stx_o_tmp <= 1'b1; |
counter <= 5'b0; |
shift_out <= 7'b0; |
bit_out <= 1'b0; |
parity_xor <= 1'b0; |
tf_pop <= 1'b0; |
bit_counter <= 3'b0; |
end |
else |
if (enable) |
246,124 → 226,124
case (tstate) |
s_idle : if (~|tf_count) // if tf_count==0 |
begin |
tstate <= #1 s_idle; |
stx_o_tmp <= #1 1'b1; |
tstate <= s_idle; |
stx_o_tmp <= 1'b1; |
end |
else |
begin |
tf_pop <= #1 1'b0; |
stx_o_tmp <= #1 1'b1; |
tstate <= #1 s_pop_byte; |
tf_pop <= 1'b0; |
stx_o_tmp <= 1'b1; |
tstate <= s_pop_byte; |
end |
s_pop_byte : begin |
tf_pop <= #1 1'b1; |
tf_pop <= 1'b1; |
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word |
2'b00 : begin |
bit_counter <= #1 3'b100; |
parity_xor <= #1 ^tf_data_out[4:0]; |
bit_counter <= 3'b100; |
parity_xor <= ^tf_data_out[4:0]; |
end |
2'b01 : begin |
bit_counter <= #1 3'b101; |
parity_xor <= #1 ^tf_data_out[5:0]; |
bit_counter <= 3'b101; |
parity_xor <= ^tf_data_out[5:0]; |
end |
2'b10 : begin |
bit_counter <= #1 3'b110; |
parity_xor <= #1 ^tf_data_out[6:0]; |
bit_counter <= 3'b110; |
parity_xor <= ^tf_data_out[6:0]; |
end |
2'b11 : begin |
bit_counter <= #1 3'b111; |
parity_xor <= #1 ^tf_data_out[7:0]; |
bit_counter <= 3'b111; |
parity_xor <= ^tf_data_out[7:0]; |
end |
endcase |
{shift_out[6:0], bit_out} <= #1 tf_data_out; |
tstate <= #1 s_send_start; |
{shift_out[6:0], bit_out} <= tf_data_out; |
tstate <= s_send_start; |
end |
s_send_start : begin |
tf_pop <= #1 1'b0; |
tf_pop <= 1'b0; |
if (~|counter) |
counter <= #1 5'b01111; |
counter <= 5'b01111; |
else |
if (counter == 5'b00001) |
begin |
counter <= #1 0; |
tstate <= #1 s_send_byte; |
counter <= 0; |
tstate <= s_send_byte; |
end |
else |
counter <= #1 counter - 1'b1; |
stx_o_tmp <= #1 1'b0; |
counter <= counter - 1'b1; |
stx_o_tmp <= 1'b0; |
end |
s_send_byte : begin |
if (~|counter) |
counter <= #1 5'b01111; |
counter <= 5'b01111; |
else |
if (counter == 5'b00001) |
begin |
if (bit_counter > 3'b0) |
begin |
bit_counter <= #1 bit_counter - 1'b1; |
{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; |
tstate <= #1 s_send_byte; |
bit_counter <= bit_counter - 1'b1; |
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; |
tstate <= s_send_byte; |
end |
else // end of byte |
if (~lcr[`UART_LC_PE]) |
begin |
tstate <= #1 s_send_stop; |
tstate <= s_send_stop; |
end |
else |
begin |
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) |
2'b00: bit_out <= #1 ~parity_xor; |
2'b01: bit_out <= #1 1'b1; |
2'b10: bit_out <= #1 parity_xor; |
2'b11: bit_out <= #1 1'b0; |
2'b00: bit_out <= ~parity_xor; |
2'b01: bit_out <= 1'b1; |
2'b10: bit_out <= parity_xor; |
2'b11: bit_out <= 1'b0; |
endcase |
tstate <= #1 s_send_parity; |
tstate <= s_send_parity; |
end |
counter <= #1 0; |
counter <= 0; |
end |
else |
counter <= #1 counter - 1'b1; |
stx_o_tmp <= #1 bit_out; // set output pin |
counter <= counter - 1'b1; |
stx_o_tmp <= bit_out; // set output pin |
end |
s_send_parity : begin |
if (~|counter) |
counter <= #1 5'b01111; |
counter <= 5'b01111; |
else |
if (counter == 5'b00001) |
begin |
counter <= #1 4'b0; |
tstate <= #1 s_send_stop; |
counter <= 4'b0; |
tstate <= s_send_stop; |
end |
else |
counter <= #1 counter - 1'b1; |
stx_o_tmp <= #1 bit_out; |
counter <= counter - 1'b1; |
stx_o_tmp <= bit_out; |
end |
s_send_stop : begin |
if (~|counter) |
begin |
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) |
3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor |
3'b100: counter <= #1 5'b10101; // 1.5 stop bit |
default: counter <= #1 5'b11101; // 2 stop bits |
3'b0xx: counter <= 5'b01101; // 1 stop bit ok igor |
3'b100: counter <= 5'b10101; // 1.5 stop bit |
default: counter <= 5'b11101; // 2 stop bits |
endcase |
end |
else |
if (counter == 5'b00001) |
begin |
counter <= #1 0; |
tstate <= #1 s_idle; |
counter <= 0; |
tstate <= s_idle; |
end |
else |
counter <= #1 counter - 1'b1; |
stx_o_tmp <= #1 1'b1; |
counter <= counter - 1'b1; |
stx_o_tmp <= 1'b1; |
end |
|
default : // should never get here |
tstate <= #1 s_idle; |
tstate <= s_idle; |
endcase |
end // end if enable |
else |
tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width |
tf_pop <= 1'b0; // tf_pop must be 1 cycle width |
end // transmitter logic |
|
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition |
/uart_sync_flops.v
61,11 → 61,8
// |
// CVS Revision History |
// |
// $Log: uart_sync_flops.v,v $ |
// Revision 1.1 2004/05/21 11:43:25 tadejm |
// Added to synchronize RX input to Wishbone clock. |
// $Log: not supported by cvs2svn $ |
// |
// |
|
|
`include "timescale.v" |