OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if
    from Rev 360 to Rev 363
    ↔ Reverse comparison
  •

Rev 360 → Rev 363

/dbg_cpu.v
39,50 → 39,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_cpu.v,v $
// Revision 1.12 2004/04/08 14:15:10 igorm
// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
// check-in.
//
// Revision 1.11 2004/04/07 19:28:55 igorm
// Zero is shifted out when CTRL_READ command is active.
//
// Revision 1.10 2004/04/01 10:22:45 igorm
// Signals for easier debugging removed.
//
// Revision 1.9 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.8 2004/03/28 20:27:01 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.7 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.6 2004/01/22 13:58:53 mohor
// Port signals are all set to zero after reset.
//
// Revision 1.5 2004/01/19 07:32:41 simons
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
//
// Revision 1.4 2004/01/17 18:38:11 mohor
// cpu_tall_o is set with cpu_stb_o or register.
//
// Revision 1.3 2004/01/17 18:01:24 mohor
// New version.
//
// Revision 1.2 2004/01/17 17:01:14 mohor
// Almost finished.
//
// Revision 1.1 2004/01/16 14:53:31 mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
285,7 → 242,10
dr[31:0] <= {dr[30:0], 1'b0};
latch_data <= 1'b0;
end
end
end
default: begin
end
endcase
end
else if (enable && (!addr_len_cnt_end))
307,7 → 267,7
else if (update_dr_i)
cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
else if (cmd_cnt_en)
cmd_cnt <= cmd_cnt + 1'b1;
cmd_cnt <= cmd_cnt + 1;
end
 
 
357,7 → 317,7
else if (update_dr_i)
addr_len_cnt <= 6'h0;
else if (addr_len_cnt_en)
addr_len_cnt <= addr_len_cnt + 1'b1;
addr_len_cnt <= addr_len_cnt + 1;
end
 
 
381,11 → 341,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (data_cnt_en)
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
end
 
 
394,9 → 354,9
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt_limit <= len + 1'b1;
data_cnt_limit <= len + 1;
end
 
 
424,7 → 384,7
if (rst_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
else if(crc_cnt_en)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
end
462,7 → 422,7
else if (update_dr_i)
status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
else if (status_cnt_en)
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + 1;
end
 
 
532,11 → 492,11
if (rst_i)
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
else if(update_dr_i)
len_var <= len + 1'b1;
len_var <= len + 'd1;
else if (start_rd_tck)
begin
if (len_var > 'd4)
len_var <= len_var - 3'd4;
if (len_var > 4)
len_var <= len_var - 'd4;
else
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
end
571,7 → 531,7
if (rst_i)
begin
start_wr_tck <= 1'b0;
cpu_dat_tmp <= 32'h0;
cpu_dat_tmp <= 32'd0;
end
else if (curr_cmd_go && acc_type_write)
begin
686,7 → 646,8
cpu_addr_dsff <= adr;
else if (cpu_ack_i && (!cpu_ack_q))
//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
cpu_addr_dsff <= cpu_addr_dsff + 3'd1; // Increment by just 1, to allow block reading -- jb 090901
// Increment by just 1, to allow block reading -- jb 090901
cpu_addr_dsff <= cpu_addr_dsff + 'd1;
end
 
 
/dbg_wb.v
39,81 → 39,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_wb.v,v $
// Revision 1.23 2004/04/01 17:21:22 igorm
// Changes for the FormalPRO.
//
// Revision 1.22 2004/04/01 11:56:59 igorm
// Port names and defines for the supported CPUs changed.
//
// Revision 1.21 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.20 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.19 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.18 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.17 2004/01/22 13:58:53 mohor
// Port signals are all set to zero after reset.
//
// Revision 1.16 2004/01/19 07:32:41 simons
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
//
// Revision 1.15 2004/01/17 18:01:24 mohor
// New version.
//
// Revision 1.14 2004/01/16 14:51:33 mohor
// cpu registers added.
//
// Revision 1.13 2004/01/15 12:09:43 mohor
// Working.
//
// Revision 1.12 2004/01/14 22:59:18 mohor
// Temp version.
//
// Revision 1.11 2004/01/14 12:29:40 mohor
// temp version. Resets will be changed in next version.
//
// Revision 1.10 2004/01/13 11:28:14 mohor
// tmp version.
//
// Revision 1.9 2004/01/10 07:50:24 mohor
// temp version.
//
// Revision 1.8 2004/01/09 12:48:44 mohor
// tmp version.
//
// Revision 1.7 2004/01/08 17:53:36 mohor
// tmp version.
//
// Revision 1.6 2004/01/07 11:58:56 mohor
// temp4 version.
//
// Revision 1.5 2004/01/06 17:15:19 mohor
// temp3 version.
//
// Revision 1.4 2004/01/05 12:16:00 mohor
// tmp2 version.
//
// Revision 1.3 2003/12/23 16:22:46 mohor
// Tmp version.
//
// Revision 1.2 2003/12/23 15:26:26 mohor
// Small fix.
//
// Revision 1.1 2003/12/23 15:09:04 mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
262,7 → 187,7
reg [2:0] mem_ptr_dsff;
reg wishbone_ce_csff;
reg mem_ptr_init;
reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
wire curr_cmd_go;
reg curr_cmd_go_q;
wire curr_cmd_wr_comm;
393,7 → 318,7
else if (update_dr_i)
cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
else if (cmd_cnt_en)
cmd_cnt <= cmd_cnt + 1'b1;
cmd_cnt <= cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
end
 
 
401,11 → 326,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
else if (update_dr_i)
curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
else if (cmd_cnt == (`DBG_WB_CMD_LEN -1))
curr_cmd <= {dr[`DBG_WB_CMD_LEN-2 :0], tdi_i};
curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
curr_cmd <= {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
end
 
 
439,11 → 364,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
addr_len_cnt <= 6'h0;
addr_len_cnt <= 6'd0;
else if (update_dr_i)
addr_len_cnt <= 6'h0;
addr_len_cnt <= 6'd0;
else if (addr_len_cnt_en)
addr_len_cnt <= addr_len_cnt + 1'b1;
addr_len_cnt <= addr_len_cnt + 6'd1;
end
 
 
467,11 → 392,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
else if (data_cnt_en)
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
end
 
 
480,9 → 405,9
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}};
data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt_limit <= len + 1'b1;
data_cnt_limit <= len + 1;
end
 
 
510,7 → 435,7
if (rst_i)
crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
else if(crc_cnt_en)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
end
548,7 → 473,7
else if (update_dr_i)
status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
else if (status_cnt_en)
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
end
 
 
615,23 → 540,23
if (rst_i)
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
else if(update_dr_i)
len_var <= len + 1'b1;
len_var <= len + 1;
else if (start_rd_tck)
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 :
if (len_var > 'd1)
len_var <= len_var - 1'd1;
len_var <= len_var - 1;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
`DBG_WB_READ16:
if (len_var > 'd2)
len_var <= len_var - 2'd2;
len_var <= len_var - 2;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
`DBG_WB_READ32:
if (len_var > 'd4)
len_var <= len_var - 3'd4;
len_var <= len_var - 4;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
default: len_var <= {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
640,7 → 565,8
end
 
 
assign len_eq_0 = len_var == 'h0;
assign len_eq_0 = !(|len_var);
 
 
assign byte = data_cnt[2:0] == 3'd7;
708,7 → 634,10
begin
start_wr_tck <= 1'b0;
end
end
end
default: begin
 
end
endcase
end
else
800,17 → 729,17
always @ (posedge wb_clk_i or posedge rst_i)
begin
if (rst_i)
wb_adr_dsff <= 32'h0;
wb_adr_dsff <= 32'd0;
else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
wb_adr_dsff <= adr;
else if (wb_ack_i)
begin
if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
wb_adr_dsff <= wb_adr_dsff + 1'd1;
wb_adr_dsff <= wb_adr_dsff + 32'd1;
else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
wb_adr_dsff <= wb_adr_dsff + 2'd2;
wb_adr_dsff <= wb_adr_dsff + 32'd2;
else
wb_adr_dsff <= wb_adr_dsff + 3'd4;
wb_adr_dsff <= wb_adr_dsff + 32'd4;
end
end
 
1021,9 → 950,9
else if (wb_ack_i)
begin
if (acc_type == `DBG_WB_READ8)
mem_ptr_dsff <= mem_ptr_dsff + 1'd1;
mem_ptr_dsff <= mem_ptr_dsff + 3'd1;
else if (acc_type == `DBG_WB_READ16)
mem_ptr_dsff <= mem_ptr_dsff + 2'd2;
mem_ptr_dsff <= mem_ptr_dsff + 3'd2;
end
end
 
1082,8 → 1011,8
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 1'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 2'd2;
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 3'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 3'd2;
`DBG_WB_READ32: fifo_cnt <= fifo_cnt + 3'd4;
default: fifo_cnt <= 3'bxxx;
endcase
1091,8 → 1020,8
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 1'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 2'd2;
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 3'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 3'd2;
`DBG_WB_READ32: fifo_cnt <= fifo_cnt - 3'd4;
default: fifo_cnt <= 3'bxxx;
endcase
/dbg_if.v
396,7 → 396,7
if (rst_i)
data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
else if(shift_dr_i & (~data_cnt_end))
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
else if (update_dr_i)
data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
end
411,7 → 411,7
if (rst_i)
crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
end
434,7 → 434,7
if (rst_i)
status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + 1;
else if (update_dr_i)
status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
end
502,7 → 502,7
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
module_dr <= `DBG_TOP_MODULE_DATA_LEN'h0;
module_dr <= 0;
else if (data_shift_en)
module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.