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    /openrisc/trunk/orpsocv2/rtl/verilog/include
    from Rev 403 to Rev 408
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  •

Rev 403 → Rev 408

/eth_defines.v
3,15 → 3,13
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// Altered by Julius Baxter, julius.baxter@orsoc.se, increasing ////
//// TX fifo buffer size, and uncommenting WB_B3 compat define ////
//// http://opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// Modified by: ////
//// - Julius Baxter (julius@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
39,144 → 37,9
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.33 2003/11/12 18:24:58 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.32 2003/10/17 07:46:13 markom
// mbist signals updated according to newest convention
//
// Revision 1.31 2003/08/14 16:42:58 simons
// Artisan ram instance added.
//
// Revision 1.30 2003/06/13 11:55:37 mohor
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
// moved from tb_eth_defines.v to eth_defines.v.
//
// Revision 1.29 2002/11/19 18:13:49 mohor
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
//
// Revision 1.28 2002/11/15 14:27:15 mohor
// Since r_Rst bit is not used any more, default value is changed to 0xa000.
//
// Revision 1.27 2002/11/01 18:19:34 mohor
// Defines fixed to use generic RAM by default.
//
// Revision 1.26 2002/10/24 18:53:03 mohor
// fpga define added.
//
// Revision 1.3 2002/10/11 16:57:54 igorm
// eth_defines.v tagged with rel_5 used.
//
// Revision 1.25 2002/10/10 16:47:44 mohor
// Defines changed to have ETH_ prolog.
// ETH_WISHBONE_B# define added.
//
// Revision 1.24 2002/10/10 16:33:11 mohor
// Bist added.
//
// Revision 1.23 2002/09/23 18:22:48 mohor
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
// core.
//
// Revision 1.22 2002/09/04 18:36:49 mohor
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
//
// Revision 1.21 2002/08/16 22:09:47 mohor
// Defines for register width added. mii_rst signal in MIIMODER register
// changed.
//
// Revision 1.20 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.19 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.18 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.17 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.16 2002/03/19 12:53:29 mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
// Revision 1.15 2002/02/26 16:11:32 mohor
// Number of interrupts changed
//
// Revision 1.14 2002/02/16 14:03:44 mohor
// Registered trimmed. Unused registers removed.
//
// Revision 1.13 2002/02/16 13:06:33 mohor
// EXTERNAL_DMA used instead of WISHBONE_DMA.
//
// Revision 1.12 2002/02/15 10:58:31 mohor
// Changed that were lost with last update put back to the file.
//
// Revision 1.11 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.10 2002/02/12 17:01:19 mohor
// HASH0 and HASH1 registers added.
 
// Revision 1.9 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.8 2002/02/05 16:44:38 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.7 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:21:37 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/11/13 14:23:56 mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
 
 
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
 
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
/i2c_master_slave_defines.v
0,0 → 1,66
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master controller defines ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
//
// $Date: 2001-11-05 11:59:25 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
 
 
// I2C registers wishbone addresses
 
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
 
`define I2C_SLAVE_CMD_WRITE 2'b01
`define I2C_SLAVE_CMD_READ 2'b10
`define I2C_SLAVE_CMD_NOP 2'b00
 
 
 
/usbhostslave_hostslave_h.v
0,0 → 1,80
//////////////////////////////////////////////////////////////////////
// usbHostSlave_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostSlave_h_vdefined
`else
`define usbHostSlave_h_vdefined
 
// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports
// control reads and writes to USB flash dongle
// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect
// time outs, added low speed EOP keep alive. The TX bit rate is now controlled by
// SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
// speed, and TX resume is always low speed.
// Fixed read clock recovery (readUSBWireData.v) issue which was resulting
// in missing receive packets.
// Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
// by adding kludged delay to softranmit. This needs to be fixed properly.
// This version has undergone limited testing
// with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
// with uClinux, and is known to work with a full speed USB flash stick.
// Moving Opencores project status from Beta to done.
// TODO: Test isochronous mode, and low speed mode using uClinux driver
// Create a seperate clock domain for the bus interface
// Add frame period adjustment capability
// Add compilation flags for slave only and host only versions
// Create data bus width options beyond 8-bit
// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
// Removed TX and RX fifo status registers, and removed
// TX fifo data count register.
// Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
// Fixed slave mode bug which caused receive fifo to be filled with
// incoming data when the slave was responding with a NAK, and the
// data should have been discarded.
// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
// Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
// there was no detected activity on the USB data lines. This caused an infrequent
// misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
// the higher level state machines are actively looking for receive packets.
// Modified USB RX data clock recovery, so that data is sampled during the middle
// of a USB bit period. Fixed a bug which could result in double sampling
// of USB RX data if clock phase adjustments were required in the middle of a
// USB packet.
// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
// during migration to ActiveHDL 7.1. Released SystemC test bench.
// Re-generated .v files using ActiveHDL 7.1
// Replaced individual timescale directives with `include "timescale.v
// Renamed top level Altera wrapper from 'usbHostSlaveWrap' to
// 'usbHostSlaveAvalonWrap'
// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
// synchronizer to incoming USB wire data to avoid
// metastability, and delay hazards. Not entirely sure, but it appears that
// this bug caused more problems with some of the newer low power FPGAs
// Maybe because they are more prone to problems with metastable
// inputs that feed logic functions causing excessive high speed
// toggle activity, and disrupting nearby cicuits.
// Version 2.0 - June 16th 2008. Added two new top level modules which
// allow the instantiation of only host (usbHost.v), or only device
// features. Added double sync stages between usbClk, and busClk domains
// to fix possible metastability issues. Also modified synchronization to
// allow operation with busClk frequency less than usbClk frequency (down to
// 24MHz). Integrated full support for USB PHY. Prior to this modification
// the user would need to instantiate a GPIO module to control USB speed,
// D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
// Modified cross-clock synchronisation of fifo resets
// Added usbDevice, a standalone usb device implementation of usbhostslave
// no additional hardware or software required
 
 
// Most significant nibble corresponds to major revision.
// Least significant nibble corresponds to minor revision.
`define USBHOSTSLAVE_VERSION_NUM 8'h20
 
//Host slave common registers
`define HOST_SLAVE_CONTROL_REG 1'b0
`define HOST_SLAVE_VERSION_REG 1'b1
 
`endif //usbHostSlave_h_vdefined
 
/usbhostslave_slavecontrol_h.v
0,0 → 1,86
//////////////////////////////////////////////////////////////////////
// usbSlaveControl.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSlaveControl_h_vdefined
`else
`define usbSlaveControl_h_vdefined
 
//endPointConstants
`define NUM_OF_ENDPOINTS 4
`define NUM_OF_REGISTERS_PER_ENDPOINT 4
`define BASE_INDEX_FOR_ENDPOINT_REGS 0
`define ENDPOINT_CONTROL_REG 0
`define ENDPOINT_STATUS_REG 1
`define ENDPOINT_TRANSTYPE_STATUS_REG 2
`define NAK_TRANSTYPE_STATUS_REG 3
`define EP0_CTRL_REG 5'h0
`define EP0_STS_REG 5'h1
`define EP0_TRAN_TYPE_STS_REG 5'h2
`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
`define EP1_CTRL_REG 5'h4
`define EP1_STS_REG 5'h5
`define EP1_TRAN_TYPE_STS_REG 5'h6
`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
`define EP2_CTRL_REG 5'h8
`define EP2_STS_REG 5'h9
`define EP2_TRAN_TYPE_STS_REG 5'ha
`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
`define EP3_CTRL_REG 5'hc
`define EP3_STS_REG 5'hd
`define EP3_TRAN_TYPE_STS_REG 5'he
`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
 
 
//SCRegIndices
`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
`define SC_CONTROL_REG 5'h10
`define SC_LINE_STATUS_REG 5'h11
`define SC_INTERRUPT_STATUS_REG 5'h12
`define SC_INTERRUPT_MASK_REG 5'h13
`define SC_ADDRESS 5'h14
`define SC_FRAME_NUM_MSP 5'h15
`define SC_FRAME_NUM_LSP 5'h16
`define SCREG_BUFFER_LEN 5'h17
//SCRXStatusRegIndices
`define NAK_SET_MASK 8'h10
`define SC_CRC_ERROR_BIT 0
`define SC_BIT_STUFF_ERROR_BIT 1
`define SC_RX_OVERFLOW_BIT 2
`define SC_RX_TIME_OUT_BIT 3
`define SC_NAK_SENT_BIT 4
`define SC_STALL_SENT_BIT 5
`define SC_ACK_RXED_BIT 6
`define SC_DATA_SEQUENCE_BIT 7
//SCEndPointControlRegIndices
`define ENDPOINT_ENABLE_BIT 0
`define ENDPOINT_READY_BIT 1
`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
`define ENDPOINT_SEND_STALL_BIT 3
`define ENDPOINT_ISO_ENABLE_BIT 4
//SCMasterControlegIndices
`define SC_GLOBAL_ENABLE_BIT 0
`define SC_TX_LINE_STATE_LSBIT 1
`define SC_TX_LINE_STATE_MSBIT 2
`define SC_DIRECT_CONTROL_BIT 3
`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
`define SC_FULL_SPEED_LINE_RATE_BIT 5
`define SC_CONNECT_TO_HOST_BIT 6
//SCinterruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define RESET_EVENT_BIT 2 //Line has entered reset state or left reset state
`define SOF_RECEIVED_BIT 3
`define NAK_SENT_INT_BIT 4
`define VBUS_DET_INT_BIT 5
//TXTransactionTypes
`define SC_SETUP_TRANS 0
`define SC_IN_TRANS 1
`define SC_OUTDATA_TRANS 2
//timeOuts
`define SC_RX_PACKET_TOUT 18
 
//line status reg
`define VBUS_PRES_BIT 2
 
`endif //usbSlaveControl_h_vdefined
/usbhostslave_constants_h.v
0,0 → 1,32
//////////////////////////////////////////////////////////////////////
//// usbConstants_h.v
///////////////////////////////////////////////////////////////////////
 
`ifdef usbConstants_h_vdefined
`else
`define usbConstants_h_vdefined
 
//PIDTypes
`define OUT 4'h1
`define IN 4'h9
`define SOF 4'h5
`define SETUP 4'hd
`define DATA0 4'h3
`define DATA1 4'hb
`define ACK 4'h2
`define NAK 4'ha
`define STALL 4'he
`define PREAMBLE 4'hc
 
//PIDGroups
`define SPECIAL 2'b00
`define TOKEN 2'b01
`define HANDSHAKE 2'b10
`define DATA 2'b11
 
// start of packet SyncByte
`define SYNC_BYTE 8'h80
 
`endif //usbConstants_h_vdefined
 
/usbhostslave_hostcontrol_h.v
0,0 → 1,75
//////////////////////////////////////////////////////////////////////
// usbHostControl_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostControl_h_vdefined
`else
`define usbHostControl_h_vdefined
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HOST_SOF_TIMER_MSB_REG 4'hf
 
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
`define ISO_ENABLE_BIT 3
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
//TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants
//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
//`define SOF_TX_MARGIN 2
`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
//Host RXStatusRegIndices
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 
`endif //usbHostControl_h_vdefined
/usbhostslave_serialinterfaceengine_h.v
0,0 → 1,108
//////////////////////////////////////////////////////////////////////
// usbSerialInterfaceEngine_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbSerialInterfaceEngine_h_vdefined
`else
`define usbSerialInterfaceEngine_h_vdefined
 
// Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
`define FS_OVER_SAMPLE_RATE 4
`define LS_OVER_SAMPLE_RATE 32
 
//timeOuts
`define RX_PACKET_TOUT 18
`define RX_EDGE_DET_TOUT 7
 
//TXStreamControlTypes
`define TX_DIRECT_CONTROL 8'h00
`define TX_RESUME_START 8'h01
`define TX_PACKET_START 8'h02
`define TX_PACKET_STREAM 8'h03
`define TX_PACKET_STOP 8'h04
`define TX_IDLE 8'h05
`define TX_LS_KEEP_ALIVE 8'h06
 
//RXStreamControlTypes
`define RX_PACKET_START 0
`define RX_PACKET_STREAM 1
`define RX_PACKET_STOP 2
 
//USBLineStates
// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
`define ONE_ZERO 2'b10
`define ZERO_ONE 2'b01
`define SE0 2'b00
`define SE1 2'b11
 
//RXStatusIndices
`define CRC_ERROR_BIT 0
`define BIT_STUFF_ERROR_BIT 1
`define RX_OVERFLOW_BIT 2
`define NAK_RXED_BIT 3
`define STALL_RXED_BIT 4
`define ACK_RXED_BIT 5
`define DATA_SEQUENCE_BIT 6
 
//usbWireControlStates
`define TRI_STATE 1'b0
`define DRIVE 1'b1
 
//limits
`define MAX_CONSEC_SAME_BITS 4'h6
`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
// RESUME_RX_WAIT_TIME defines the time period for resume detection
// The resume counter is incremented at the bit rate, so
// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
// and 30 * 1/1.5MHz = 20uS at low speed, both of which are within the USB spec of
// 2.5uS <= resumeDetectTime <= 100uS
`define RESUME_RX_WAIT_TIME 5'd29
//`define RESUME_WAIT_TIME_MINUS1 9
// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate
`ifdef SIM_COMPILE
`define HOST_TX_RESUME_TIME 16'd10
`else
`define HOST_TX_RESUME_TIME 16'd30000 //Host sends resume for 30000 * 1/1.5MHz = 20mS
`endif
//`define CONNECT_WAIT_TIME 8'd20
`define CONNECT_WAIT_TIME 8'd120 //Device connect detected after 120 * 1/48MHz = 2.5uS
//`define DISCONNECT_WAIT_TIME 8'd20
`define DISCONNECT_WAIT_TIME 8'd120 //Device disconnect detected after 120 * 1/48MHz = 2.5uS
 
//RXConnectStates
`define DISCONNECT 2'b00
`define LOW_SPEED_CONNECT 2'b01
`define FULL_SPEED_CONNECT 2'b10
 
//TX_RX_InternalStreamTypes
`define DATA_START 8'h00
`define DATA_STOP 8'h01
`define DATA_STREAM 8'h02
`define DATA_BIT_STUFF_ERROR 8'h03
 
//RXStMach states
`define DISCONNECT_ST 4'h0
`define WAIT_FULL_SPEED_CONN_ST 4'h1
`define WAIT_LOW_SPEED_CONN_ST 4'h2
`define CONNECT_LOW_SPEED_ST 4'h3
`define CONNECT_FULL_SPEED_ST 4'h4
`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
 
//RXBitStateMachStates
`define IDLE_BIT_ST 2'b00
`define DATA_RECEIVE_BIT_ST 2'b01
`define WAIT_RESUME_ST 2'b10
`define RESUME_END_WAIT_ST 2'b11
 
//RXByteStateMachStates
`define IDLE_BYTE_ST 3'b000
`define CHECK_SYNC_ST 3'b001
`define CHECK_PID_ST 3'b010
`define HS_BYTE_ST 3'b011
`define TOKEN_BYTE_ST 3'b100
`define DATA_BYTE_ST 3'b101
 
`endif //usbSerialInterfaceEngine_h_vdefined
 
 
/usbhostslave_wishbonebus_h.v
0,0 → 1,35
//////////////////////////////////////////////////////////////////////
// wishBoneBus_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef wishBoneBus_h_vdefined
`else
`define wishBoneBus_h_vdefined
//memoryMap
`define HCREG_BASE 8'h00
`define HCREG_BASE_PLUS_0X10 8'h10
`define HOST_RX_FIFO_BASE 8'h20
`define HOST_TX_FIFO_BASE 8'h30
`define SCREG_BASE 8'h40
`define SCREG_BASE_PLUS_0X10 8'h50
`define EP0_RX_FIFO_BASE 8'h60
`define EP0_TX_FIFO_BASE 8'h70
`define EP1_RX_FIFO_BASE 8'h80
`define EP1_TX_FIFO_BASE 8'h90
`define EP2_RX_FIFO_BASE 8'ha0
`define EP2_TX_FIFO_BASE 8'hb0
`define EP3_RX_FIFO_BASE 8'hc0
`define EP3_TX_FIFO_BASE 8'hd0
`define HOST_SLAVE_CONTROL_BASE 8'he0
`define ADDRESS_DECODE_MASK 8'hf0
 
//FifoAddresses
`define FIFO_DATA_REG 3'b000
`define FIFO_STATUS_REG 3'b001
`define FIFO_DATA_COUNT_MSB 3'b010
`define FIFO_DATA_COUNT_LSB 3'b011
`define FIFO_CONTROL_REG 3'b100
 
`endif //wishBoneBus_h_vdefined
 

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