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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb
- from Rev 546 to Rev 655
- ↔ Reverse comparison
Rev 546 → Rev 655
/ram_wb_b3.v
1,3 → 1,4
//`include "synthesis-defines.v" |
module ram_wb_b3( |
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i, |
wb_stb_i, wb_we_i, |
119,7 → 120,7
If not Verilator model, always do load, otherwise only load when called |
from SystemC testbench. |
*/ |
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// synthesis translate_off |
parameter memory_file = "sram.vmem"; |
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`ifdef verilator |
135,9 → 136,11
begin |
$readmemh(memory_file, mem); |
end |
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`endif // !`ifdef verilator |
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`endif // !`ifdef verilator |
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//synthesis translate_on |
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assign wb_rty_o = 0; |
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// mux for data to ram, RMW on part sel != 4'hf |
209,9 → 212,9
// Error signal generation |
// |
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// Error when out of bounds of memory - skip top byte of address in case |
// this is mapped somewhere other than 0x00. |
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]); |
// Error when out of bounds of memory - skip top nibble of address in case |
// this is mapped somewhere other than 0x0. |
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-4:mem_adr_width]); |
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// OR in other errors here... |
assign wb_err_o = wb_ack_o_r & wb_stb_i & |