URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog
- from Rev 356 to Rev 358
- ↔ Reverse comparison
Rev 356 → Rev 358
/or1200_defines.v
175,6 → 175,11
// |
|
// |
// Reset active low |
// |
//`define OR1200_RST_ACT_LOW |
|
// |
// Enable RAM BIST |
// |
// At the moment this only works for Virtual Silicon |
426,6 → 431,17
//`define OR1200_IMPL_MEM2REG2 |
|
// |
// Reset value and event |
// |
`ifdef OR1200_RST_ACT_LOW |
`define OR1200_RST_VALUE (1'b0) |
`define OR1200_RST_EVENT negedge |
`else |
`define OR1200_RST_VALUE (1'b1) |
`define OR1200_RST_EVENT posedge |
`endif |
|
// |
// ALUOPs |
// |
`define OR1200_ALUOP_WIDTH 4 |
535,13 → 551,13
// Bit 0: register file write enable |
// Bits 3-1: write-back mux selects |
// |
`define OR1200_RFWBOP_WIDTH 4 |
`define OR1200_RFWBOP_NOP 4'b0000 |
`define OR1200_RFWBOP_ALU 3'b000 |
`define OR1200_RFWBOP_LSU 3'b001 |
`define OR1200_RFWBOP_SPRS 3'b010 |
`define OR1200_RFWBOP_LR 3'b011 |
`define OR1200_RFWBOP_FPU 3'b100 |
`define OR1200_RFWBOP_WIDTH 4 |
`define OR1200_RFWBOP_NOP 4'b0000 |
`define OR1200_RFWBOP_ALU 3'b000 |
`define OR1200_RFWBOP_LSU 3'b001 |
`define OR1200_RFWBOP_SPRS 3'b010 |
`define OR1200_RFWBOP_LR 3'b011 |
`define OR1200_RFWBOP_FPU 3'b100 |
|
// Compare instructions |
`define OR1200_COP_SFEQ 3'b000 |
/components/or1200/or1200_spram_1024x8.v
383,8 → 383,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_freeze.v
139,8 → 139,8
// |
// registered flushpipe |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
flushpipe_r <= 1'b0; |
else if (icpu_ack_i | icpu_err_i) |
// else if (!if_stall) |
156,8 → 156,8
// |
// Multicycle counter |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
multicycle_cnt <= 2'b00; |
else if (|multicycle_cnt) |
multicycle_cnt <= multicycle_cnt - 2'd1; |
168,8 → 168,8
// |
// Waiting on generation |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
waiting_on <= 0; |
else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done) |
waiting_on <= 0; |
/components/or1200/or1200_qmem_top.v
319,8 → 319,8
// |
// QMEM control FSM |
// |
always @(posedge rst or posedge clk) |
if (rst) begin |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) begin |
state <= `OR1200_QMEMFSM_IDLE; |
qmem_dack <= 1'b0; |
qmem_iack <= 1'b0; |
/components/or1200/or1200_spram_2048x32_bw.v
636,8 → 636,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= 11'h000; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_tt.v
151,8 → 151,8
// Write to TTMR or update of TTMR[IP] bit |
// |
`ifdef OR1200_TT_TTMR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
ttmr <= 32'b0; |
else if (ttmr_sel && spr_write) |
ttmr <= spr_dat_i; |
166,8 → 166,8
// Write to or increment of TTCR |
// |
`ifdef OR1200_TT_TTCR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
ttcr <= 32'b0; |
else if (restart) |
ttcr <= 32'b0; |
/components/or1200/or1200_sprs.v
327,8 → 327,8
// |
// Supervision register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1}; |
else if (except_started) |
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0]; |
336,9 → 336,9
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0]; |
|
// EPH part of Supervision register |
always @(posedge clk or posedge rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
// default value |
if (rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
sr_reg_bit_eph <= `OR1200_SR_EPH_DEF; |
sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state |
end |
/components/or1200/or1200_immu_top.v
251,9 → 251,9
// icpu_adr_o |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge rst or posedge clk) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
// default value |
if (rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
icpu_adr_default <= 32'h0000_0100; |
icpu_adr_select <= 1'b1; // select async. value due to reset state |
end |
290,8 → 290,8
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come |
// one clock cycle after offset part. |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}}; |
else |
icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS]; |
337,8 → 337,8
// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and |
// icpu_rty_o clears it. |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dis_spr_access_frst_clk <= 1'b0; |
else if (!icpu_rty_o) |
dis_spr_access_frst_clk <= 1'b0; |
345,8 → 345,8
else if (spr_cs) |
dis_spr_access_frst_clk <= 1'b1; |
|
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dis_spr_access_scnd_clk <= 1'b0; |
else if (!icpu_rty_o) |
dis_spr_access_scnd_clk <= 1'b0; |
377,8 → 377,8
// Assert itlb_en_r after one clock cycle and when there is no |
// ITLB SPR access |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
itlb_en_r <= 1'b0; |
else |
itlb_en_r <= itlb_en & ~itlb_spr_access; |
422,8 → 422,8
// |
// spr_dat_o is registered on the 1st clock of spr read |
// so itlb can continue with process during execution of mfspr. |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
spr_dat_reg <= 32'h0000_0000; |
else if (spr_cs & !dis_spr_access_scnd_clk) |
spr_dat_reg <= itlb_dat_o; |
/components/or1200/or1200_fpu.v
193,8 → 193,8
fpu_op_r <= {1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]}; |
|
// Indicate new FPU op |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
fpu_op_valid_re <= 0; |
else if (fpu_op_valid_re) |
fpu_op_valid_re <= 0; |
204,8 → 204,8
// |
// FPCSR system group register implementation |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
fpcsr_r <= 0; |
else |
begin |
236,7 → 236,7
if (except_started) |
fpcsr_r[`OR1200_FPCSR_FPEE] <= 0; |
end // else: !if(rst) |
end // always @ (posedge clk or posedge rst) |
end // always @ (posedge clk or `OR1200_RST_EVENT rst) |
|
// |
// Comparison flag generation |
/components/or1200/or1200_dc_fsm.v
359,8 → 359,8
// |
// Main DC FSM |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
state <= `OR1200_DCFSM_IDLE; |
addr_r <= 32'b0; |
hitmiss_eval <= 1'b0; |
555,7 → 555,7
|
endcase // case (state) |
|
end // always @ (posedge clk or posedge rst) |
end // always @ (posedge clk or `OR1200_RST_EVENT rst) |
|
|
endmodule |
/components/or1200/or1200_sb.v
149,8 → 149,8
// |
// SB enable |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
sb_en_reg <= 1'b0; |
else if (sb_en & ~dcsb_cyc_i) |
sb_en_reg <= 1'b1; // enable SB when there is no dcsb transfer in progress |
174,8 → 174,8
// |
// fifo_rd |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
outstanding_store <= 1'b0; |
else if (sbbiu_ack_i) |
outstanding_store <= 1'b0; |
185,8 → 185,8
// |
// fifo_wr_ack |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
fifo_wr_ack <= 1'b0; |
else if (fifo_wr) |
fifo_wr_ack <= 1'b1; |
/components/or1200/or1200_dpram_32x32.v
309,8 → 309,8
|
reg [4:0] addr_a_r; |
|
always @(posedge clk_a or posedge rst_a) |
if (rst_a) |
always @(posedge clk_a or `OR1200_RST_EVENT rst_a) |
if (rst_a == `OR1200_RST_VALUE) |
addr_a_r <= 5'b00000; |
else if (ce_a) |
addr_a_r <= addr_a; |
532,8 → 532,8
// |
// RAM read |
// |
always @(posedge clk_a or posedge rst_a) |
if (rst_a) |
always @(posedge clk_a or `OR1200_RST_EVENT rst_a) |
if (rst_a == `OR1200_RST_VALUE) |
addr_a_reg <= {aw{1'b0}}; |
else if (ce_a) |
addr_a_reg <= addr_a; |
/components/or1200/or1200_sb_fifo.v
94,8 → 94,8
reg empty_o; |
reg full_o; |
|
always @(posedge clk_i or posedge rst_i) |
if (rst_i) begin |
always @(posedge clk_i or `OR1200_RST_EVENT rst_i) |
if (rst_i == `OR1200_RST_VALUE) begin |
full_o <= 1'b0; |
empty_o <= 1'b1; |
wr_pntr <= {fw{1'b0}}; |
/components/or1200/or1200_spram_256x21.v
399,8 → 399,8
// |
// RAM adress register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_spram_2048x8.v
409,8 → 409,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_tpram_32x32.v
401,8 → 401,8
// |
// RAM read address register |
// |
always @(posedge clk_a or posedge rst_a) |
if (rst_a) |
always @(posedge clk_a or `OR1200_RST_EVENT rst_a) |
if (rst_a == `OR1200_RST_VALUE) |
addr_a_reg <= {aw{1'b0}}; |
else if (ce_a) |
addr_a_reg <= addr_a; |
410,8 → 410,8
// |
// RAM read address register |
// |
always @(posedge clk_b or posedge rst_b) |
if (rst_b) |
always @(posedge clk_b or `OR1200_RST_EVENT rst_b) |
if (rst_b == `OR1200_RST_VALUE) |
addr_b_reg <= {aw{1'b0}}; |
else if (ce_b) |
addr_b_reg <= addr_b; |
/components/or1200/or1200_lsu.v
130,8 → 130,8
// |
// ex_lsu_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_lsu_op <= `OR1200_LSUOP_NOP; |
else if (!ex_freeze & id_freeze | flushpipe) |
ex_lsu_op <= `OR1200_LSUOP_NOP; |
145,8 → 145,8
assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] + |
id_addrofs[`OR1200_LSUEA_PRECALC-1:0]; |
|
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}}; |
else if (!ex_freeze) |
dcpu_adr_r <= id_precalc_sum; |
155,8 → 155,8
// |
// Generate except_align in ID stage |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
except_align <= 1'b0; |
else if (!ex_freeze & id_freeze | flushpipe) |
except_align <= 1'b0; |
/components/or1200/or1200_ctrl.v
216,8 → 216,8
// next different is DS insn, previous different was Jump/Branch |
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
ex_delayslot_nop <= 1'b0; |
ex_delayslot_dsi <= 1'b0; |
end |
248,8 → 248,8
// |
// EX Sign/Zero extension of immediates |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_simm <= 32'h0000_0000; |
else if (!ex_freeze) begin |
ex_simm <= id_simm; |
319,8 → 319,8
// |
|
// pipeline ID and EX branch target address |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_branch_addrtarget <= 32'h00000000; |
else if (!ex_freeze) |
ex_branch_addrtarget <= id_branch_addrtarget; |
350,8 → 350,8
// l.macrc in EX stage |
// |
`ifdef OR1200_MAC_IMPLEMENTED |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_macrc_op <= 1'b0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
ex_macrc_op <= 1'b0; |
516,8 → 516,8
// |
// Register file write address |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
rf_addrw <= 5'd0; |
else if (!ex_freeze & id_freeze) |
rf_addrw <= 5'd00; |
533,8 → 533,8
// |
// rf_addrw in wb stage (used in forwarding logic) |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
wb_rfaddrw <= 5'd0; |
else if (!wb_freeze) |
wb_rfaddrw <= rf_addrw; |
543,8 → 543,8
// |
// Instruction latch in id_insn |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; |
else if (id_flushpipe) |
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1 |
561,8 → 561,8
// |
// Instruction latch in ex_insn |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1 |
579,8 → 579,8
// |
// Instruction latch in wb_insn |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
wb_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; |
// wb_insn should not be changed by exceptions due to correct |
// recording of display_arch_state in the or1200_monitor! |
593,8 → 593,8
// |
// Decode of sel_imm |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
sel_imm <= 1'b0; |
else if (!id_freeze) begin |
case (if_insn[31:26]) // synopsys parallel_case |
676,8 → 676,8
// |
// Decode of except_illegal |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
except_illegal <= 1'b0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
except_illegal <= 1'b0; |
774,8 → 774,8
// |
// Decode of alu_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
alu_op <= `OR1200_ALUOP_NOP; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
alu_op <= `OR1200_ALUOP_NOP; |
847,8 → 847,8
// |
// Decode of spr_read, spr_write |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
spr_read <= 1'b0; |
spr_write <= 1'b0; |
end |
903,8 → 903,8
endcase |
end |
|
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
ex_mac_op <= `OR1200_MACOP_NOP; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
ex_mac_op <= `OR1200_MACOP_NOP; |
921,8 → 921,8
// |
// Decode of shrot_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
shrot_op <= `OR1200_SHROTOP_NOP; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
shrot_op <= `OR1200_SHROTOP_NOP; |
934,8 → 934,8
// |
// Decode of rfwb_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
rfwb_op <= `OR1200_RFWBOP_NOP; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
rfwb_op <= `OR1200_RFWBOP_NOP; |
1034,8 → 1034,8
// |
// Decode of id_branch_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
id_branch_op <= `OR1200_BRANCHOP_NOP; |
else if (id_flushpipe) |
id_branch_op <= `OR1200_BRANCHOP_NOP; |
1081,8 → 1081,8
// |
// Generation of ex_branch_op |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
ex_branch_op <= `OR1200_BRANCHOP_NOP; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
ex_branch_op <= `OR1200_BRANCHOP_NOP; |
1137,8 → 1137,8
// |
// Decode of comp_op |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
comp_op <= 4'd0; |
end else if (!ex_freeze & id_freeze | ex_flushpipe) |
comp_op <= 4'd0; |
1160,8 → 1160,8
// |
// Decode of l.sys |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
sig_syscall <= 1'b0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
sig_syscall <= 1'b0; |
1179,8 → 1179,8
// |
// Decode of l.trap |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
sig_trap <= 1'b0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
sig_trap <= 1'b0; |
1199,8 → 1199,8
// Decode destination register address for data cache to check if store ops |
// are being done from the stack register (r1) or frame pointer register (r2) |
`ifdef OR1200_DC_NOSTACKWRITETHROUGH |
always @(posedge clk or posedge rst) begin |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
dc_no_writethrough <= 0; |
else if (!ex_freeze) |
dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2); |
/components/or1200/or1200_wb_biu.v
185,8 → 185,8
// |
// WB FSM - register part |
// |
always @(posedge wb_clk_i or posedge wb_rst_i) begin |
if (wb_rst_i) |
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin |
if (wb_rst_i == `OR1200_RST_VALUE) |
wb_fsm_state_cur <= wb_fsm_idle; |
else |
wb_fsm_state_cur <= wb_fsm_state_nxt; |
195,8 → 195,8
// |
// WB burst tength counter |
// |
always @(posedge wb_clk_i or posedge wb_rst_i) begin |
if (wb_rst_i) begin |
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin |
if (wb_rst_i == `OR1200_RST_VALUE) begin |
burst_len <= 2'h0; |
end |
else begin |
277,8 → 277,8
// |
// WB FSM - output signals |
// |
always @(posedge wb_clk_i or posedge wb_rst_i) begin |
if (wb_rst_i) begin |
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin |
if (wb_rst_i == `OR1200_RST_VALUE) begin |
wb_cyc_o <= 1'b0; |
wb_stb_o <= 1'b0; |
wb_cti_o <= 3'b111; |
329,8 → 329,8
// |
// WB & BIU termination toggle counters |
// |
always @(posedge wb_clk_i or posedge wb_rst_i) begin |
if (wb_rst_i) begin |
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin |
if (wb_rst_i == `OR1200_RST_VALUE) begin |
wb_ack_cnt <= 1'b0; |
wb_err_cnt <= 1'b0; |
wb_rty_cnt <= 1'b0; |
354,8 → 354,8
end |
end |
|
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
biu_stb_reg <= 1'b0; |
biu_ack_cnt <= 1'b0; |
biu_err_cnt <= 1'b0; |
/components/or1200/or1200_rf.v
191,8 → 191,8
// |
// RF write enable is either from SPRS or normal from CPU control |
// |
always @(posedge rst or posedge clk) |
if (rst) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) |
rf_we_allow <= 1'b1; |
else if (~wb_freeze) |
rf_we_allow <= ~flushpipe; |
/components/or1200/or1200_du.v
141,8 → 141,8
// |
// Show insn activity (temp, must be removed) |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dbg_is_o <= 2'b00; |
else if (!ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16])) |
dbg_is_o <= ~dbg_is_o; |
168,8 → 168,8
// |
// Generate acknowledge -- just delay stb signal |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
dbg_ack <= 1'b0; |
dbg_ack_o <= 1'b0; |
end |
586,8 → 586,8
// |
// Breakpoint activation register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dbg_bp_r <= 1'b0; |
else if (!ex_freeze) |
dbg_bp_r <= |except_stop |
605,8 → 605,8
// Write to DMR1 |
// |
`ifdef OR1200_DU_DMR1 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dmr1 <= 25'h000_0000; |
else if (dmr1_sel && spr_write) |
`ifdef OR1200_DU_HWBKPTS |
622,8 → 622,8
// Write to DMR2 |
// |
`ifdef OR1200_DU_DMR2 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dmr2 <= 24'h00_0000; |
else if (dmr2_sel && spr_write) |
dmr2 <= spr_dat_i[23:0]; |
635,8 → 635,8
// Write to DSR |
// |
`ifdef OR1200_DU_DSR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}}; |
else if (dsr_sel && spr_write) |
dsr <= spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0]; |
648,8 → 648,8
// Write to DRR |
// |
`ifdef OR1200_DU_DRR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
drr <= 14'b0; |
else if (drr_sel && spr_write) |
drr <= spr_dat_i[13:0]; |
663,8 → 663,8
// Write to DVR0 |
// |
`ifdef OR1200_DU_DVR0 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr0 <= 32'h0000_0000; |
else if (dvr0_sel && spr_write) |
dvr0 <= spr_dat_i[31:0]; |
676,8 → 676,8
// Write to DVR1 |
// |
`ifdef OR1200_DU_DVR1 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr1 <= 32'h0000_0000; |
else if (dvr1_sel && spr_write) |
dvr1 <= spr_dat_i[31:0]; |
689,8 → 689,8
// Write to DVR2 |
// |
`ifdef OR1200_DU_DVR2 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr2 <= 32'h0000_0000; |
else if (dvr2_sel && spr_write) |
dvr2 <= spr_dat_i[31:0]; |
702,8 → 702,8
// Write to DVR3 |
// |
`ifdef OR1200_DU_DVR3 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr3 <= 32'h0000_0000; |
else if (dvr3_sel && spr_write) |
dvr3 <= spr_dat_i[31:0]; |
715,8 → 715,8
// Write to DVR4 |
// |
`ifdef OR1200_DU_DVR4 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr4 <= 32'h0000_0000; |
else if (dvr4_sel && spr_write) |
dvr4 <= spr_dat_i[31:0]; |
728,8 → 728,8
// Write to DVR5 |
// |
`ifdef OR1200_DU_DVR5 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr5 <= 32'h0000_0000; |
else if (dvr5_sel && spr_write) |
dvr5 <= spr_dat_i[31:0]; |
741,8 → 741,8
// Write to DVR6 |
// |
`ifdef OR1200_DU_DVR6 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr6 <= 32'h0000_0000; |
else if (dvr6_sel && spr_write) |
dvr6 <= spr_dat_i[31:0]; |
754,8 → 754,8
// Write to DVR7 |
// |
`ifdef OR1200_DU_DVR7 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dvr7 <= 32'h0000_0000; |
else if (dvr7_sel && spr_write) |
dvr7 <= spr_dat_i[31:0]; |
767,8 → 767,8
// Write to DCR0 |
// |
`ifdef OR1200_DU_DCR0 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr0 <= 8'h00; |
else if (dcr0_sel && spr_write) |
dcr0 <= spr_dat_i[7:0]; |
780,8 → 780,8
// Write to DCR1 |
// |
`ifdef OR1200_DU_DCR1 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr1 <= 8'h00; |
else if (dcr1_sel && spr_write) |
dcr1 <= spr_dat_i[7:0]; |
793,8 → 793,8
// Write to DCR2 |
// |
`ifdef OR1200_DU_DCR2 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr2 <= 8'h00; |
else if (dcr2_sel && spr_write) |
dcr2 <= spr_dat_i[7:0]; |
806,8 → 806,8
// Write to DCR3 |
// |
`ifdef OR1200_DU_DCR3 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr3 <= 8'h00; |
else if (dcr3_sel && spr_write) |
dcr3 <= spr_dat_i[7:0]; |
819,8 → 819,8
// Write to DCR4 |
// |
`ifdef OR1200_DU_DCR4 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr4 <= 8'h00; |
else if (dcr4_sel && spr_write) |
dcr4 <= spr_dat_i[7:0]; |
832,8 → 832,8
// Write to DCR5 |
// |
`ifdef OR1200_DU_DCR5 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr5 <= 8'h00; |
else if (dcr5_sel && spr_write) |
dcr5 <= spr_dat_i[7:0]; |
845,8 → 845,8
// Write to DCR6 |
// |
`ifdef OR1200_DU_DCR6 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr6 <= 8'h00; |
else if (dcr6_sel && spr_write) |
dcr6 <= spr_dat_i[7:0]; |
858,8 → 858,8
// Write to DCR7 |
// |
`ifdef OR1200_DU_DCR7 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcr7 <= 8'h00; |
else if (dcr7_sel && spr_write) |
dcr7 <= spr_dat_i[7:0]; |
871,8 → 871,8
// Write to DWCR0 |
// |
`ifdef OR1200_DU_DWCR0 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dwcr0 <= 32'h0000_0000; |
else if (dwcr0_sel && spr_write) |
dwcr0 <= spr_dat_i[31:0]; |
886,8 → 886,8
// Write to DWCR1 |
// |
`ifdef OR1200_DU_DWCR1 |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dwcr1 <= 32'h0000_0000; |
else if (dwcr1_sel && spr_write) |
dwcr1 <= spr_dat_i[31:0]; |
1620,8 → 1620,8
`endif |
|
// Hold du_hwbkpt if ex_freeze is active in order to cause trap exception |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
du_hwbkpt_hold <= 1'b0; |
else if (du_hwbkpt & ex_freeze) |
du_hwbkpt_hold <= 1'b1; |
1645,8 → 1645,8
// |
// Trace buffer write address pointer |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
tb_wadr <= 8'h00; |
else if (tb_enw) |
tb_wadr <= tb_wadr + 8'd1; |
1654,8 → 1654,8
// |
// Free running counter (time stamp) |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
tb_timstmp <= 32'h00000000; |
else if (!dbg_bp_r) |
tb_timstmp <= tb_timstmp + 32'd1; |
/components/or1200/or1200_pm.v
135,8 → 135,8
// Write to PMR and also PMR[DME]/PMR[SME] reset when |
// pic_wakeup is asserted |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
{dcge, sme, dme, sdf} <= 7'b0; |
else if (pmr_sel && spr_write) begin |
sdf <= spr_dat_i[`OR1200_PM_PMR_SDF]; |
/components/or1200/or1200_spram_32x24.v
290,8 → 290,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_amultp2_32x32.v
779,8 → 779,8
input CLK; |
output DOUT; |
reg DOUT_reg; |
always @ ( posedge RST or posedge CLK ) begin |
if (RST) |
always @ ( `OR1200_RST_EVENT RST or posedge CLK ) begin |
if (RST == `OR1200_RST_VALUE) |
DOUT_reg <= 1'b0; |
else |
DOUT_reg <= DIN; |
2357,8 → 2357,8
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) ); |
assign INT_CARRY[0] = LOGIC_ZERO; |
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(ARESULT[0:63]), .COUT() ); |
always @(posedge CLK or posedge RST) |
if (RST) |
always @(posedge CLK or `OR1200_RST_EVENT RST) |
if (RST == `OR1200_RST_VALUE) |
RESULT <= 64'h0000_0000_0000_0000; |
else |
RESULT <= ARESULT; |
/components/or1200/or1200_spram_1024x32.v
512,8 → 512,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_spram_64x22.v
391,8 → 391,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_spram_64x24.v
393,8 → 393,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_gmultp2_32x32.v
116,8 → 116,8
// |
// First multiply stage |
// |
always @(posedge CLK or posedge RST) |
if (RST) |
always @(posedge CLK or `OR1200_RST_EVENT RST) |
if (RST == `OR1200_RST_VALUE) |
p0 <= `OR1200_WW'b0; |
else |
p0 <= xi * yi; |
125,8 → 125,8
// |
// Second multiply stage |
// |
always @(posedge CLK or posedge RST) |
if (RST) |
always @(posedge CLK or `OR1200_RST_EVENT RST) |
if (RST == `OR1200_RST_VALUE) |
p1 <= `OR1200_WW'b0; |
else |
p1 <= p0; |
/components/or1200/or1200_dpram_256x32.v
200,8 → 200,8
// |
// RAM read |
// |
always @(posedge clk_a or posedge rst_a) |
if (rst_a) |
always @(posedge clk_a or `OR1200_RST_EVENT rst_a) |
if (rst_a == `OR1200_RST_VALUE) |
addr_a_reg <= {aw{1'b0}}; |
else if (ce_a) |
addr_a_reg <= addr_a; |
/components/or1200/or1200_spram_2048x32.v
616,8 → 616,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_if.v
118,8 → 118,8
// |
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe; |
|
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
if_bypass_reg <= 1'b0; |
else |
if_bypass_reg <= if_bypass; |
138,8 → 138,8
// |
// Flag for saved insn/address |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
saved <= 1'b0; |
else if (if_flushpipe) |
saved <= 1'b0; |
151,8 → 151,8
// |
// Store fetched instruction |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000}; |
else if (if_flushpipe) |
insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000}; |
164,8 → 164,8
// |
// Store fetched instruction's address |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_saved <= 32'h00000000; |
else if (if_flushpipe) |
addr_saved <= 32'h00000000; |
177,8 → 177,8
// |
// Store fetched instruction's error tags |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
err_saved <= 3'b000; |
else if (if_flushpipe) |
err_saved <= 3'b000; |
/components/or1200/or1200_mult_mac.v
219,8 → 219,8
// Registered output from the multiplier and |
// an optional divider |
// |
always @(posedge rst or posedge clk) |
if (rst) begin |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) begin |
mul_prod_r <= 64'h0000_0000_0000_0000; |
div_free <= 1'b1; |
`ifdef OR1200_DIV_IMPLEMENTED |
256,8 → 256,8
// Signal to indicate when we should check for new MAC op |
reg ex_freeze_r; |
|
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
ex_freeze_r <= 1'b1; |
else |
ex_freeze_r <= ex_freeze; |
265,8 → 265,8
// |
// Propagation of l.mac opcode, only register it for one cycle |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
mac_op_r1 <= `OR1200_MACOP_WIDTH'b0; |
else |
mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0; |
274,8 → 274,8
// |
// Propagation of l.mac opcode |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
mac_op_r2 <= `OR1200_MACOP_WIDTH'b0; |
else |
mac_op_r2 <= mac_op_r1; |
283,8 → 283,8
// |
// Propagation of l.mac opcode |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
mac_op_r3 <= `OR1200_MACOP_WIDTH'b0; |
else |
mac_op_r3 <= mac_op_r2; |
292,8 → 292,8
// |
// Implementation of MAC |
// |
always @(posedge rst or posedge clk) |
if (rst) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) |
mac_r <= 64'h0000_0000_0000_0000; |
`ifdef OR1200_MAC_SPR_WE |
else if (spr_maclo_we) |
313,8 → 313,8
// in EX stage (e.g. inside multiplier) |
// This stall signal is also used by the divider. |
// |
always @(posedge rst or posedge clk) |
if (rst) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) |
mac_stall_r <= 1'b0; |
else |
mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r) |
/components/or1200/or1200_wbmux.v
97,8 → 97,8
// |
// Registered output from the write-back multiplexer |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
muxreg <= 32'd0; |
muxreg_valid <= 1'b0; |
end |
/components/or1200/or1200_spram_128x32.v
264,8 → 264,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_operandmuxes.v
94,8 → 94,8
// |
// Operand A register |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
operand_a <= 32'd0; |
saved_a <= 1'b0; |
end else if (!ex_freeze && id_freeze && !saved_a) begin |
110,8 → 110,8
// |
// Operand B register |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
operand_b <= 32'd0; |
saved_b <= 1'b0; |
end else if (!ex_freeze && id_freeze && !saved_b) begin |
/components/or1200/or1200_pic.v
116,8 → 116,8
// Write to PICMR |
// |
`ifdef OR1200_PIC_PICMR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}}; |
else if (picmr_sel && spr_write) begin |
picmr <= spr_dat_i[`OR1200_PIC_INTS-1:2]; |
130,8 → 130,8
// Write to PICSR, both CPU and external ints |
// |
`ifdef OR1200_PIC_PICSR |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
picsr <= {`OR1200_PIC_INTS{1'b0}}; |
else if (picsr_sel && spr_write) begin |
picsr <= spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints; |
/components/or1200/or1200_spram_1024x32_bw.v
532,8 → 532,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= 10'h000; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_dmmu_top.v
206,8 → 206,8
// |
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dtlb_done <= 1'b0; |
else if (dtlb_en) |
dtlb_done <= dcpu_cycstb_i; |
231,8 → 231,8
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is |
// expected to come one clock cycle after offset part. |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
dcpu_vpn_r <= {31-`OR1200_DMMU_PS{1'b0}}; |
else |
dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS]; |
/components/or1200/or1200_except.v
266,8 → 266,8
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze |
}; |
|
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
trace_trap <= 1'b0 ; |
end |
else if (!(trace_trap && !ex_pc_val)) begin |
275,8 → 275,8
end |
end |
|
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
ex_freeze_prev <= 1'b0 ; |
sr_ted_prev <= 1'b0 ; |
dsr_te_prev <= 1'b0 ; |
332,8 → 332,8
// |
// PC and Exception flags pipelines |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
id_pc <= 32'd0; |
id_pc_val <= 1'b0 ; |
id_exceptflags <= 3'b000; |
357,8 → 357,8
// together with SR[IEE] enables interrupts once |
// pipeline is again ready. |
// |
always @(posedge rst or posedge clk) |
if (rst) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) |
delayed_iee <= 3'b000; |
else if (!sr[`OR1200_SR_IEE]) |
delayed_iee <= 3'b000; |
373,8 → 373,8
// together with SR[TEE] enables tick exceptions once |
// pipeline is again ready. |
// |
always @(posedge rst or posedge clk) |
if (rst) |
always @(`OR1200_RST_EVENT rst or posedge clk) |
if (rst == `OR1200_RST_VALUE) |
delayed_tee <= 3'b000; |
else if (!sr[`OR1200_SR_TEE]) |
delayed_tee <= 3'b000; |
384,8 → 384,8
// |
// PC and Exception flags pipelines |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
ex_dslot <= 1'b0; |
ex_pc <= 32'd0; |
ex_pc_val <= 1'b0 ; |
421,8 → 421,8
// |
// PC and Exception flags pipelines |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
wb_pc <= 32'd0; |
dl_pc <= 32'd0; |
end |
445,8 → 445,8
// except_type signals which exception handler we start fetching in: |
// 1. Asserted in next clock cycle after exception is recognized |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
state <= `OR1200_EXCEPTFSM_IDLE; |
except_type <= `OR1200_EXCEPT_NONE; |
extend_flush <= 1'b0; |
/components/or1200/or1200_spram_64x14.v
376,8 → 376,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |
/components/or1200/or1200_genpc.v
138,8 → 138,8
// |
// genpc_freeze_r |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
genpc_refetch_r <= 1'b0; |
else if (genpc_refetch) |
genpc_refetch_r <= 1'b1; |
255,9 → 255,9
// |
// PC register |
// |
always @(posedge clk or posedge rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
// default value |
if (rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
pcreg_default <= `OR1200_BOOT_PCREG_DEFAULT; // jb |
pcreg_select <= 1'b1;// select async. value due to reset state |
end |
/components/or1200/or1200_ic_fsm.v
136,8 → 136,8
// |
// Main IC FSM |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) begin |
state <= `OR1200_ICFSM_IDLE; |
saved_addr_r <= 32'b0; |
hitmiss_eval <= 1'b0; |
/components/or1200/or1200_rfram_generic.v
154,8 → 154,8
// |
// Write port |
// |
always @(posedge clk or posedge rst) |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) begin |
mem <= {512'h0, 512'h0}; |
end |
else if (ce_w & we_w) |
200,8 → 200,8
// |
// Read port A |
// |
always @(posedge clk or posedge rst) |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) begin |
intaddr_a <= 5'h00; |
end |
else if (ce_a) |
249,8 → 249,8
// |
// Read port B |
// |
always @(posedge clk or posedge rst) |
if (rst) begin |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) begin |
intaddr_b <= 5'h00; |
end |
else if (ce_b) |
/components/or1200/or1200_spram_512x20.v
409,8 → 409,8
// |
// RAM address register |
// |
always @(posedge clk or posedge rst) |
if (rst) |
always @(posedge clk or `OR1200_RST_EVENT rst) |
if (rst == `OR1200_RST_VALUE) |
addr_reg <= {aw{1'b0}}; |
else if (ce) |
addr_reg <= addr; |