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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog
    from Rev 43 to Rev 44
    ↔ Reverse comparison
  •

Rev 43 → Rev 44

/components/smii/smii_sync.v
43,7 → 43,7
// SMII sync
output sync,
// internal
output reg [10:1] state, // Changed for verilator -- jb
output reg [10:1] state,
// clock amd reset
input clk,
input rst
52,7 → 52,7
// sync shall go high every 10:th cycle
always @ (posedge clk or posedge rst)
if (rst)
state <= 10'b1000000000;
state <= 10'b0000000001;
else
state <= {state[9:1],state[10]};
 
/components/smii/smii_txrx.v
66,7 → 66,7
output reg link,
`endif
// internal
input [10:1] state, // Change bit size declaration order, was [1:10], not verilator compatible: %Error: Unsupported: MSB < LSB of bit range: 1<10
input [10:1] state,
// clock and reset
input clk,
input rst
112,14 → 112,27
/////////////////////////////////////////////////
// Transmit
 
/* Timing scheme:
On the first clock of segment 0 (so each segment when 100Mb/s,
fast ethernet, or every 10 segments for 10Mb/s ethernet) we
deteremine if that segment is data or not, depending on what is
in the tx_data_reg_valid register. If the MAC wants to transmit
something, we overwrite the previously sent values when they're
no longer needed. Once the first nibble is sent, we can then
overwrite it, and same for the second - so we generate the TX
clock when state is 5, and sample the new nibble on the next
clock, same with the second nibble, that is clocked when state
is 9, and sampled when it is 10, so it gets overwritten when
we've finished putting it on the serial line.*/
always @ (posedge clk or posedge rst)
if (rst)
mtx_clk_tmp <= 1'b0;
else
if ((state[10] | state[5]) & (tx_cnt == 4'd0))
if ((state[5] | state[9]) & (tx_cnt == 4'd0))
mtx_clk_tmp <= 1'b1;
else if (state[2] | state[7])
else if (state[6] | state[10])
mtx_clk_tmp <= 1'b0;
 
`ifdef ACTEL
141,26 → 154,32
a0 <= 1'b0;
end
else
if ((state[4] | state[9]) & (tx_cnt == 4'd0))
if ((state[6] | state[10]) & (tx_cnt == 4'd0))
begin
/* Toggale a0 when MII TX_EN goes high */
if (!mtxen)
a0 <= 1'b0;
else
a0 <= ~a0;
 
/* byte will be valid when MII TX_EN
is high from the MAC */
if (!mtxen & !a0)
tx_data_reg_valid <= 1'b0;
else if (a0)
tx_data_reg_valid <= 1'b1;
 
/* Sample the nibble */
if (mtxen & !a0)
//tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
tx_data_reg[3:0] <= {mtxd[3],mtxd[2],mtxd[1],mtxd[0]}; // Changed for verilator -- jb
tx_data_reg[3:0] <= mtxd;
else if (mtxen & a0)
//tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
tx_data_reg[7:4] <= {mtxd[3],mtxd[2],mtxd[1],mtxd[0]}; // Changed for verilator -- jb
tx_data_reg[7:4] <= mtxd;
end // if ((state[4] | state[9]) & (tx_cnt == 4'd0))
 
// state flag
/* Determine if we output a data byte or the inter-frame sequence
with status information */
always @ (posedge clk or posedge rst)
if (rst)
state_data <= 1'b0;
167,11 → 186,18
else
if (state[1] & (tx_cnt == 4'd0))
state_data <= tx_data_reg_valid;
 
/* A wire hooked up from bit 0 with the last byte of the state counter/shiftreg */
wire [7:0] state_data_byte;
assign state_data_byte[7:0] = state[10:3];
/* Assign the SMII TX wire */
/* First bit always TX_ERR, then depending on the next bit, TX_EN, output
either the inter-frame status byte or a data byte */
assign tx = state[1] ? mtxerr :
state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
state_data ? |(state[10:2] & tx_data_reg) : // changed bit select order to 10:2 -- jb
|(state[10:2] & {mtxerr,speed,duplex,link,jabber,3'b111}); // changed bit select order to 10:2 -- jb
state_data ? |(state_data_byte & tx_data_reg) :
|(state_data_byte & {3'b111,jabber,link,duplex,speed,mtxerr});
 
/////////////////////////////////////////////////
// Receive
199,20 → 225,33
end
else
begin
/* Continually shift rx into rx_tmp bit 2, and shift rx_tmp along */
rx_tmp[2:0] <= {rx,rx_tmp[2:1]};
 
/* We appear to be beginning our sampling when state bit 3 is set */
if (state[3])
mcrs <= rx;
/* rx_tmp[3] is used as the RX_DV bit*/
if (state[4])
rx_tmp[3] <= rx;
if (rx_tmp[3]) //rxdv
 
if (rx_tmp[3]) //If data byte valid, and when we've got the first nibble, output it */
begin
/* At this stage we've got the first 3 bits of the bottom
nibble - we can sample the rx line directly to get the
4th, and we'll also indicate that this byte is valid by
raising the MII RX data valid (dv) line. */
if (state[8])
{mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};
/* High nibble, we have 3 bits and the final one is on
the line - put it out for the MAC to read.*/
else if (state[2])
mrxd <= #1 {rx,rx_tmp[2:0]};
end
else
begin
/* Not a data byte, it's the inter-frame status byte */
if (state[5])
mrxerr <= #1 rx;
if (state[6])
248,6 → 287,7
assign #1 mrx_clk = mrx_clk_tmp;
`endif
assign mcoll = mcrs & mtxen;
assign mcoll = mcrs & mtxen & !duplex;
endmodule // smii_top
/components/or1200r2/or1200_sprs.v
155,9 → 155,9
input [width-1:0] dat_i; // SPR write data
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
input [width-1:0] epcr /* verilator public */; // EPCR0
input [width-1:0] eear /* verilator public */; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
input except_started; // Exception was started
output [width-1:0] to_wbmux; // For l.mfspr
output epcr_we; // EPCR0 write enable
166,7 → 166,7
output pc_we; // PC write enable
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
404,6 → 404,33
always @(sr_reg or sr_reg_bit_eph_muxed)
sr = {sr_reg[`OR1200_SR_WIDTH-1], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-3:0]};
 
`ifdef verilator
// Function to access various sprs (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
 
function [31:0] get_sr;
// verilator public
get_sr = sr;
endfunction // get_sr
 
function [31:0] get_epcr;
// verilator public
get_epcr = epcr;
endfunction // get_epcr
 
function [31:0] get_eear;
// verilator public
get_eear = eear;
endfunction // get_eear
 
function [31:0] get_esr;
// verilator public
get_esr = esr;
endfunction // get_esr
 
`endif
 
//
// MTSPR/MFSPR interface
//
/components/or1200r2/or1200_except.v
228,7 → 228,7
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
reg [31:0] id_pc;
reg [31:0] ex_pc;
reg [31:0] wb_pc;
reg [31:0] wb_pc /* verilator public */;
reg [31:0] epcr;
reg [31:0] eear;
reg [`OR1200_SR_WIDTH-1:0] esr;
237,12 → 237,12
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
reg extend_flush;
reg extend_flush_last;
reg ex_dslot;
reg ex_dslot /* verilator public */;
reg delayed1_ex_dslot;
reg delayed2_ex_dslot;
wire except_started;
wire [12:0] except_trig;
wire except_flushpipe;
wire except_flushpipe /* verilator public */;
reg [2:0] delayed_iee;
reg [2:0] delayed_tee;
wire int_pending;
294,6 → 294,18
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
 
`ifdef verilator
// Function to access wb_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_wb_pc;
// verilator public
get_wb_pc = wb_pc;
endfunction // get_wb_pc
 
`endif
 
 
//
// PC and Exception flags pipelines
//
/components/or1200r2/or1200_dpram.v
86,7 → 86,7
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] mem [(1<<aw)-1:0] /* verilator public */; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
 
 
96,22 → 96,7
// verilator public
input [aw-1:0] gpr_no;
 
get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
mem[gpr_no*32 + 9], mem[gpr_no*32 + 8],
mem[gpr_no*32 + 7], mem[gpr_no*32 + 6],
mem[gpr_no*32 + 5], mem[gpr_no*32 + 4],
mem[gpr_no*32 + 3], mem[gpr_no*32 + 2],
mem[gpr_no*32 + 1], mem[gpr_no*32 + 0] };
get_gpr = mem[gpr_no];
endfunction // get_gpr
/components/uart16550/uart_top.v
141,204 → 141,204
`include "uart_defines.v"
 
module uart_top (
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
int_o, // interrupt request
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
int_o, // interrupt request
 
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
 
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
, baud_o
`endif
);
);
 
parameter uart_data_width = `UART_DATA_WIDTH;
parameter uart_addr_width = `UART_ADDR_WIDTH;
parameter uart_data_width = `UART_DATA_WIDTH;
parameter uart_addr_width = `UART_ADDR_WIDTH;
 
input wb_clk_i;
input wb_clk_i;
 
// WISHBONE interface
input wb_rst_i;
input [uart_addr_width-1:0] wb_adr_i;
input [uart_data_width-1:0] wb_dat_i;
output [uart_data_width-1:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_ack_o;
output int_o;
// WISHBONE interface
input wb_rst_i;
input [uart_addr_width-1:0] wb_adr_i;
input [uart_data_width-1:0] wb_dat_i;
output [uart_data_width-1:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_ack_o;
output int_o;
 
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
 
// optional baudrate output
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
output baud_o;
`endif
 
 
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
 
wire [uart_addr_width-1:0] wb_adr_i;
wire [uart_data_width-1:0] wb_dat_i;
wire [uart_data_width-1:0] wb_dat_o;
wire [uart_addr_width-1:0] wb_adr_i;
wire [uart_data_width-1:0] wb_dat_i;
wire [uart_data_width-1:0] wb_dat_o;
 
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [uart_addr_width-1:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [uart_addr_width-1:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
 
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface wires
wire [3:0] ier;
wire [3:0] iir;
wire [1:0] fcr;
wire [4:0] mcr;
wire [7:0] lcr;
wire [7:0] msr;
wire [7:0] lsr;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
// debug interface wires
wire [3:0] ier;
wire [3:0] iir;
wire [1:0] fcr;
wire [4:0] mcr;
wire [7:0] lcr;
wire [7:0] msr;
wire [7:0] lsr;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
`endif
 
`ifdef DATA_BUS_WIDTH_8
//// WISHBONE interface module
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
//// WISHBONE interface module
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`else
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_sel_i(wb_sel_i),
.wb_dat32_o(wb_dat32_o),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
uart_wb wb_interface(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_sel_i(wb_sel_i),
.wb_dat32_o(wb_dat32_o),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
`endif
 
// Registers
uart_regs regs(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
// Registers
uart_regs regs(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
.ier(ier),
.iir(iir),
.fcr(fcr),
.mcr(mcr),
.lcr(lcr),
.msr(msr),
.lsr(lsr),
.rf_count(rf_count),
.tf_count(tf_count),
.tstate(tstate),
.rstate(rstate),
// debug interface signals enabled
.ier(ier),
.iir(iir),
.fcr(fcr),
.mcr(mcr),
.lcr(lcr),
.msr(msr),
.lsr(lsr),
.rf_count(rf_count),
.tf_count(tf_count),
.tstate(tstate),
.rstate(rstate),
`endif
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
, .baud_o(baud_o)
`endif
 
);
);
 
`ifdef DATA_BUS_WIDTH_8
`else
uart_debug_if dbg(/*AUTOINST*/
// Outputs
.wb_dat32_o (wb_dat32_o[31:0]),
// Inputs
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
.ier (ier[3:0]),
.iir (iir[3:0]),
.fcr (fcr[1:0]),
.mcr (mcr[4:0]),
.lcr (lcr[7:0]),
.msr (msr[7:0]),
.lsr (lsr[7:0]),
.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
.tstate (tstate[2:0]),
.rstate (rstate[3:0]));
uart_debug_if dbg(/*AUTOINST*/
// Outputs
.wb_dat32_o (wb_dat32_o[31:0]),
// Inputs
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
.ier (ier[3:0]),
.iir (iir[3:0]),
.fcr (fcr[1:0]),
.mcr (mcr[4:0]),
.lcr (lcr[7:0]),
.msr (msr[7:0]),
.lsr (lsr[7:0]),
.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
.tstate (tstate[2:0]),
.rstate (rstate[3:0]));
`endif
 
initial
begin
initial
begin
`ifdef UART16550_SIM_OUTPUT
`ifdef DATA_BUS_WIDTH_8
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
$display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
`else
$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
$display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
`endif
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
`endif
end
end
 
endmodule // uart_top
 
/orpsoc_top.v
1,4 → 1,46
//module ref_design_top
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc_top.v ////
//// ////
//// This file is part of the ORPSoCv2 project ////
//// http://opencores.org/openrisc/?orpsocv2 ////
//// ////
//// This is the top level RTL file for ORPSoCv2 ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB michael.unneback@orsoc.se ////
//// - Julius Baxter, julius.baxter@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008, 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
module orpsoc_top
(
output spi_sd_sclk_pad_o ,
24,7 → 66,7
output spi_flash_w_n_pad_o ,
output spi_flash_hold_n_pad_o,
`endif // `ifdef USE_SDRAM
`ifdef USE_ETHERNET
`ifdef USE_ETHERNET_IO
output [1:1] eth_sync_pad_o,
output [1:1] eth_tx_pad_o,
input [1:1] eth_rx_pad_i,
31,7 → 73,7
input eth_clk_pad_i,
inout [1:1] eth_md_pad_io,
output [1:1] eth_mdc_pad_o,
`endif // `ifdef USE_ETHERNET
`endif // `ifdef USE_ETHERNET_IO
output spi1_mosi_pad_o,
input spi1_miso_pad_i,
output spi1_ss_pad_o ,
349,7 → 391,7
assign pic_ints[7] = 1'b0;
assign pic_ints[6] = 1'b0;
assign pic_ints[5] = 1'b0;
assign pic_ints[4] = 1'b0;
assign pic_ints[4] = eth_int[1]; /* IRQ4, just like in Linux. Added jb 090716 */
assign pic_ints[3] = 1'b0;
assign pic_ints[2] = uart0_irq;
assign pic_ints[1] = 1'b0;
550,8 → 592,7
wire m1rxerr;
wire m1coll;
wire m1crs;
//wire [1:10] state;
wire [10:1] state; // Changed for verilator -- jb
wire [10:1] state;
wire sync;
wire [1:1] rx, tx;
wire [1:1] mdc_o, md_i, md_o, md_oe;
602,6 → 643,8
.md_padoe_o(md_oe[1]),
.int_o(eth_int[1])
);
 
`ifdef USE_ETHERNET_IO
iobuftri iobuftri1
(
.i(md_o[1]),
632,6 → 675,7
.clk(eth_clk),
.rst(wb_rst)
);
 
obufdff obufdff_sync1
(
.d(sync),
653,6 → 697,8
.clk(eth_clk),
.rst(wb_rst)
);
`endif // `ifdef USE_ETHERNET_IO
 
`else // !`ifdef USE_ETHERNET
// If ethernet core is disabled, still ack anyone who tries
// to access its config port. This allows linux to boot in

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